Fix up instruction classes for Thumb2 RSB instructions to be consistent with

[oota-llvm.git] / lib / CodeGen / PHIElimination.cpp

diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 165171998dbe6695f978148752b655eedf57a0ba..edbc13f3ff7f9dfbcb5e6a55d6f90b07c342a556 100644 (file)
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -27,10 +27,8 @@
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
 #include <algorithm>
 #include <map>
 using namespace llvm;
@@ -88,10 +86,6 @@ bool llvm::PHIElimination::runOnMachineFunction(MachineFunction &MF) {
   ImpDefs.clear();
   VRegPHIUseCount.clear();
 
-  // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
-  // SSA form.
-  Changed |= EliminateRegSequences(MF);
-
   return Changed;
 }
 
@@ -216,7 +210,8 @@ void llvm::PHIElimination::LowerAtomicPHINode(
     } else {
       entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
     }
-    TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
+    TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC,
+                      MPhi->getDebugLoc());
   }
 
   // Update live variable information if there is any.
@@ -298,7 +293,8 @@ void llvm::PHIElimination::LowerAtomicPHINode(
 
     // Insert the copy.
     if (!reusedIncoming && IncomingReg)
-      TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
+      TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC,
+                        MPhi->getDebugLoc());
 
     // Now update live variable information if we have it.  Otherwise we're done
     if (!LV) continue;
@@ -449,58 +445,3 @@ MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
 
   return NMBB;
 }
-
-static void UpdateRegSequenceSrcs(unsigned SrcReg,
-                                  unsigned DstReg, unsigned SrcIdx,
-                                  MachineRegisterInfo *MRI) {
-  for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
-         UE = MRI->reg_end(); RI != UE; ) {
-    MachineOperand &MO = RI.getOperand();
-    ++RI;
-    MO.setReg(DstReg);
-    MO.setSubReg(SrcIdx);
-  }
-}
-
-/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as second part
-/// of de-ssa process. This replaces sources of REG_SEQUENCE as sub-register
-/// references of the register defined by REG_SEQUENCE. e.g.
-///
-/// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
-/// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
-/// =>
-/// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
-bool PHIElimination::EliminateRegSequences(MachineFunction &MF) {
-  bool Changed = false;
-
-  for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
-    for (MachineBasicBlock::iterator BBI = I->begin(), BBE = I->end();
-         BBI != BBE; ) {
-      MachineInstr &MI = *BBI;
-      ++BBI;
-      if (MI.getOpcode() != TargetOpcode::REG_SEQUENCE)
-        continue;
-      unsigned DstReg = MI.getOperand(0).getReg();
-      if (MI.getOperand(0).getSubReg() ||
-          TargetRegisterInfo::isPhysicalRegister(DstReg) ||
-          !(MI.getNumOperands() & 1)) {
-        DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
-        llvm_unreachable(0);
-      }
-      for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
-        unsigned SrcReg = MI.getOperand(i).getReg();
-        if (MI.getOperand(i).getSubReg() ||
-            TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
-          DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
-          llvm_unreachable(0);
-        }
-        unsigned SrcIdx = MI.getOperand(i+1).getImm();
-        UpdateRegSequenceSrcs(SrcReg, DstReg, SrcIdx, MRI);
-      }
-
-      MI.eraseFromParent();
-      Changed = true;
-    }
-
-  return Changed;
-}