Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty

[oota-llvm.git] / lib / CodeGen / PostRASchedulerList.cpp

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 7bf3b3c3423ccedb555f00fdf1bb08c8adeb71bb..94b6be19fbad35d1077d60fb1e834791c5697e18 100644 (file)
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -19,8 +19,8 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "post-RA-sched"
+#include "ScheduleDAGInstrs.h"
 #include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/ScheduleDAGInstrs.h"
 #include "llvm/CodeGen/LatencyPriorityQueue.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/CodeGen/MachineDominators.h"
@@ -189,15 +189,17 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
        MBB != MBBe; ++MBB) {
     // Schedule each sequence of instructions not interrupted by a label
     // or anything else that effectively needs to shut down scheduling.
-    MachineBasicBlock::iterator Current = MBB->begin(), End = MBB->end();
-    for (MachineBasicBlock::iterator MI = Current; MI != End; ++MI)
+    MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin();
+    for (MachineBasicBlock::iterator I = Current; I != Top; ) {
+      MachineInstr *MI = --I;
       if (MI->getDesc().isTerminator() || MI->isLabel()) {
-        Scheduler.Run(0, MBB, Current, MI);
+        Scheduler.Run(0, MBB, next(I), Current);
         Scheduler.EmitSchedule();
-        Current = next(MI);
+        Current = I;
       }
+    }
 
-    Scheduler.Run(0, MBB, Current, End);
+    Scheduler.Run(0, MBB, Top, Current);
     Scheduler.EmitSchedule();
   }
 
@@ -235,12 +237,11 @@ void SchedulePostRATDList::Schedule() {
 /// instruction of the specified TargetInstrDesc.
 static const TargetRegisterClass*
 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
-                        const TargetInstrInfo *TII, const TargetInstrDesc &II,
-                        unsigned Op) {
+                         const TargetInstrDesc &II, unsigned Op) {
   if (Op >= II.getNumOperands())
     return NULL;
   if (II.OpInfo[Op].isLookupPtrRegClass())
-    return TII->getPointerRegClass();
+    return TRI->getPointerRegClass();
   return TRI->getRegClass(II.OpInfo[Op].RegClass);
 }
 
@@ -415,10 +416,10 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
   // instructions from the bottom up, tracking information about liveness
   // as we go to help determine which registers are available.
   bool Changed = false;
-  unsigned Count = BB->size() - 1;
-  for (MachineBasicBlock::reverse_iterator I = BB->rbegin(), E = BB->rend();
-       I != E; ++I, --Count) {
-    MachineInstr *MI = &*I;
+  unsigned Count = SUnits.size() - 1;
+  for (MachineBasicBlock::iterator I = End, E = Begin;
+       I != E; --Count) {
+    MachineInstr *MI = --I;
 
     // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
     // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
@@ -488,7 +489,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
       unsigned Reg = MO.getReg();
       if (Reg == 0) continue;
       const TargetRegisterClass *NewRC =
-        getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
+        getInstrOperandRegClass(TRI, MI->getDesc(), i);
 
       // If this instruction has a use of AntiDepReg, breaking it
       // is invalid.
@@ -623,7 +624,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
       if (!MO.isUse()) continue;
 
       const TargetRegisterClass *NewRC =
-        getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
+        getInstrOperandRegClass(TRI, MI->getDesc(), i);
 
       // For now, only allow the register to be changed if its register
       // class is consistent across all uses.