//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "post-RA-sched"
+#include "ScheduleDAGInstrs.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/LatencyPriorityQueue.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/DenseSet.h"
-#include "llvm/ADT/SmallVector.h"
#include <map>
-#include <climits>
using namespace llvm;
+STATISTIC(NumNoops, "Number of noops inserted");
STATISTIC(NumStalls, "Number of pipeline stalls");
static cl::opt<bool>
EnableAntiDepBreaking("break-anti-dependencies",
- cl::desc("Break scheduling anti-dependencies"),
- cl::init(true));
+ cl::desc("Break post-RA scheduling anti-dependencies"),
+ cl::init(true), cl::Hidden);
+
+static cl::opt<bool>
+EnablePostRAHazardAvoidance("avoid-hazards",
+ cl::desc("Enable simple hazard-avoidance"),
+ cl::init(true), cl::Hidden);
namespace {
class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
/// Topo - A topological ordering for SUnits.
ScheduleDAGTopologicalSort Topo;
+ /// AllocatableSet - The set of allocatable registers.
+ /// We'll be ignoring anti-dependencies on non-allocatable registers,
+ /// because they may not be safe to break.
+ const BitVector AllocatableSet;
+
+ /// HazardRec - The hazard recognizer to use.
+ ScheduleHazardRecognizer *HazardRec;
+
public:
- SchedulePostRATDList(MachineBasicBlock *mbb, const TargetMachine &tm,
+ SchedulePostRATDList(MachineFunction &MF,
const MachineLoopInfo &MLI,
- const MachineDominatorTree &MDT)
- : ScheduleDAGInstrs(mbb, tm, MLI, MDT), Topo(SUnits) {}
+ const MachineDominatorTree &MDT,
+ ScheduleHazardRecognizer *HR)
+ : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
+ AllocatableSet(TRI->getAllocatableSet(MF)),
+ HazardRec(HR) {}
+
+ ~SchedulePostRATDList() {
+ delete HazardRec;
+ }
void Schedule();
void ListScheduleTopDown();
bool BreakAntiDependencies();
};
+
+ /// SimpleHazardRecognizer - A *very* simple hazard recognizer. It uses
+ /// a coarse classification and attempts to avoid that instructions of
+ /// a given class aren't grouped too densely together.
+ class SimpleHazardRecognizer : public ScheduleHazardRecognizer {
+ /// Class - A simple classification for SUnits.
+ enum Class {
+ Other, Load, Store
+ };
+
+ /// Window - The Class values of the most recently issued
+ /// instructions.
+ Class Window[8];
+
+ /// getClass - Classify the given SUnit.
+ Class getClass(const SUnit *SU) {
+ const MachineInstr *MI = SU->getInstr();
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (TID.mayLoad())
+ return Load;
+ if (TID.mayStore())
+ return Store;
+ return Other;
+ }
+
+ /// Step - Rotate the existing entries in Window and insert the
+ /// given class value in position as the most recent.
+ void Step(Class C) {
+ std::copy(Window+1, array_endof(Window), Window);
+ Window[array_lengthof(Window)-1] = C;
+ }
+
+ public:
+ SimpleHazardRecognizer() : Window() {}
+
+ virtual HazardType getHazardType(SUnit *SU) {
+ Class C = getClass(SU);
+ if (C == Other)
+ return NoHazard;
+ unsigned Score = 0;
+ for (unsigned i = 0; i != array_lengthof(Window); ++i)
+ if (Window[i] == C)
+ Score += i + 1;
+ if (Score > array_lengthof(Window) * 2)
+ return Hazard;
+ return NoHazard;
+ }
+
+ virtual void EmitInstruction(SUnit *SU) {
+ Step(getClass(SU));
+ }
+
+ virtual void AdvanceCycle() {
+ Step(Other);
+ }
+ };
}
bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
+ ScheduleHazardRecognizer *HR = EnablePostRAHazardAvoidance ?
+ new SimpleHazardRecognizer :
+ new ScheduleHazardRecognizer();
+
+ SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR);
// Loop over all of the basic blocks
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) {
+ // Schedule each sequence of instructions not interrupted by a label
+ // or anything else that effectively needs to shut down scheduling.
+ MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin();
+ for (MachineBasicBlock::iterator I = Current; I != Top; ) {
+ MachineInstr *MI = --I;
+ if (MI->getDesc().isTerminator() || MI->isLabel()) {
+ Scheduler.Run(0, MBB, next(I), Current);
+ Scheduler.EmitSchedule();
+ Current = I;
+ }
+ }
- SchedulePostRATDList Scheduler(MBB, Fn.getTarget(), MLI, MDT);
-
- Scheduler.Run();
-
+ Scheduler.Run(0, MBB, Top, Current);
Scheduler.EmitSchedule();
}
void SchedulePostRATDList::Schedule() {
DOUT << "********** List Scheduling **********\n";
- // Build scheduling units.
- BuildSchedUnits();
+ // Build the scheduling graph.
+ BuildSchedGraph();
if (EnableAntiDepBreaking) {
if (BreakAntiDependencies()) {
// that register, and add new anti-dependence and output-dependence
// edges based on the next live range of the register.
SUnits.clear();
- BuildSchedUnits();
+ BuildSchedGraph();
}
}
/// instruction of the specified TargetInstrDesc.
static const TargetRegisterClass*
getInstrOperandRegClass(const TargetRegisterInfo *TRI,
- const TargetInstrInfo *TII, const TargetInstrDesc &II,
- unsigned Op) {
+ const TargetInstrDesc &II, unsigned Op) {
if (Op >= II.getNumOperands())
return NULL;
if (II.OpInfo[Op].isLookupPtrRegClass())
- return TII->getPointerRegClass();
+ return TRI->getPointerRegClass();
return TRI->getRegClass(II.OpInfo[Op].RegClass);
}
bool SchedulePostRATDList::BreakAntiDependencies() {
// The code below assumes that there is at least one instruction,
// so just duck out immediately if the block is empty.
- if (BB->empty()) return false;
+ if (SUnits.empty()) return false;
// Find the node at the bottom of the critical path.
SUnit *Max = 0;
}
DOUT << "Critical path has total latency "
- << (Max ? Max->getDepth() + Max->Latency : 0) << "\n";
+ << (Max->getDepth() + Max->Latency) << "\n";
- // Walk the critical path from the bottom up. Collect all anti-dependence
- // edges on the critical path. Skip anti-dependencies between SUnits that
- // are connected with other edges, since such units won't be able to be
- // scheduled past each other anyway.
- //
- // The heuristic is that edges on the critical path are more important to
- // break than other edges. And since there are a limited number of
- // registers, we don't want to waste them breaking edges that aren't
- // important.
- //
- // TODO: Instructions with multiple defs could have multiple
- // anti-dependencies. The current code here only knows how to break one
- // edge per instruction. Note that we'd have to be able to break all of
- // the anti-dependencies in an instruction in order to be effective.
- BitVector AllocatableSet = TRI->getAllocatableSet(*MF);
- DenseMap<MachineInstr *, unsigned> CriticalAntiDeps;
- SUnit *SU = Max;
- for (SDep *Edge = CriticalPathStep(SU); Edge;
- Edge = CriticalPathStep(SU = Edge->getSUnit())) {
- SUnit *NextSU = Edge->getSUnit();
- // Only consider anti-dependence edges.
- if (Edge->getKind() != SDep::Anti)
- continue;
- unsigned AntiDepReg = Edge->getReg();
- assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
- // Don't break anti-dependencies on non-allocatable registers.
- if (!AllocatableSet.test(AntiDepReg))
- continue;
- // If the SUnit has other dependencies on the SUnit that it
- // anti-depends on, don't bother breaking the anti-dependency.
- // Also, if there are dependencies on other SUnits with the
- // same register as the anti-dependency, don't attempt to
- // break it.
- for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
- P != PE; ++P)
- if (P->getSUnit() == NextSU ?
- (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
- (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
- AntiDepReg = 0;
- break;
- }
- if (AntiDepReg != 0)
- CriticalAntiDeps[SU->getInstr()] = AntiDepReg;
- }
+ // Track progress along the critical path through the SUnit graph as we walk
+ // the instructions.
+ SUnit *CriticalPathSU = Max;
+ MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
// For live regs that are only used in one register class in a live range,
// the register class. If the register is not live, the corresponding value
// Map registers to all their references within a live range.
std::multimap<unsigned, MachineOperand *> RegRefs;
- // The index of the most recent kill (proceding bottom-up), or -1 if
+ // The index of the most recent kill (proceding bottom-up), or ~0u if
// the register is not live.
unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
- std::fill(KillIndices, array_endof(KillIndices), -1);
- // The index of the most recent def (proceding bottom up), or -1 if
+ std::fill(KillIndices, array_endof(KillIndices), ~0u);
+ // The index of the most recent complete def (proceding bottom up), or ~0u if
// the register is live.
unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
std::fill(DefIndices, array_endof(DefIndices), BB->size());
// Determine the live-out physregs for this block.
- if (!BB->empty() && BB->back().getDesc().isReturn())
+ if (BB->back().getDesc().isReturn())
// In a return block, examine the function live-out regs.
for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
E = MRI.liveout_end(); I != E; ++I) {
unsigned Reg = *I;
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[Reg] = BB->size();
- DefIndices[Reg] = -1;
+ DefIndices[Reg] = ~0u;
// Repeat, for all aliases.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[AliasReg] = BB->size();
- DefIndices[AliasReg] = -1;
+ DefIndices[AliasReg] = ~0u;
}
}
else
unsigned Reg = *I;
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[Reg] = BB->size();
- DefIndices[Reg] = -1;
+ DefIndices[Reg] = ~0u;
// Repeat, for all aliases.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[AliasReg] = BB->size();
- DefIndices[AliasReg] = -1;
+ DefIndices[AliasReg] = ~0u;
}
}
// TODO: If the callee saves and restores these, then we can potentially
// use them between the save and the restore. To do that, we could scan
// the exit blocks to see which of these registers are defined.
- // Alternatively, calle-saved registers that aren't saved and restored
+ // Alternatively, callee-saved registers that aren't saved and restored
// could be marked live-in in every block.
for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
unsigned Reg = *I;
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[Reg] = BB->size();
- DefIndices[Reg] = -1;
+ DefIndices[Reg] = ~0u;
// Repeat, for all aliases.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[AliasReg] = BB->size();
- DefIndices[AliasReg] = -1;
+ DefIndices[AliasReg] = ~0u;
}
}
// instructions from the bottom up, tracking information about liveness
// as we go to help determine which registers are available.
bool Changed = false;
- unsigned Count = BB->size() - 1;
- for (MachineBasicBlock::reverse_iterator I = BB->rbegin(), E = BB->rend();
- I != E; ++I, --Count) {
- MachineInstr *MI = &*I;
+ unsigned Count = SUnits.size() - 1;
+ for (MachineBasicBlock::iterator I = End, E = Begin;
+ I != E; --Count) {
+ MachineInstr *MI = --I;
// After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
// dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
continue;
- // Check if this instruction has an anti-dependence that we're
- // interested in.
- DenseMap<MachineInstr *, unsigned>::iterator C = CriticalAntiDeps.find(MI);
- unsigned AntiDepReg = C != CriticalAntiDeps.end() ?
- C->second : 0;
+ // Check if this instruction has a dependence on the critical path that
+ // is an anti-dependence that we may be able to break. If it is, set
+ // AntiDepReg to the non-zero register associated with the anti-dependence.
+ //
+ // We limit our attention to the critical path as a heuristic to avoid
+ // breaking anti-dependence edges that aren't going to significantly
+ // impact the overall schedule. There are a limited number of registers
+ // and we want to save them for the important edges.
+ //
+ // TODO: Instructions with multiple defs could have multiple
+ // anti-dependencies. The current code here only knows how to break one
+ // edge per instruction. Note that we'd have to be able to break all of
+ // the anti-dependencies in an instruction in order to be effective.
+ unsigned AntiDepReg = 0;
+ if (MI == CriticalPathMI) {
+ if (SDep *Edge = CriticalPathStep(CriticalPathSU)) {
+ SUnit *NextSU = Edge->getSUnit();
+
+ // Only consider anti-dependence edges.
+ if (Edge->getKind() == SDep::Anti) {
+ AntiDepReg = Edge->getReg();
+ assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
+ // Don't break anti-dependencies on non-allocatable registers.
+ if (!AllocatableSet.test(AntiDepReg))
+ AntiDepReg = 0;
+ else {
+ // If the SUnit has other dependencies on the SUnit that it
+ // anti-depends on, don't bother breaking the anti-dependency
+ // since those edges would prevent such units from being
+ // scheduled past each other regardless.
+ //
+ // Also, if there are dependencies on other SUnits with the
+ // same register as the anti-dependency, don't attempt to
+ // break it.
+ for (SUnit::pred_iterator P = CriticalPathSU->Preds.begin(),
+ PE = CriticalPathSU->Preds.end(); P != PE; ++P)
+ if (P->getSUnit() == NextSU ?
+ (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
+ (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
+ AntiDepReg = 0;
+ break;
+ }
+ }
+ }
+ CriticalPathSU = NextSU;
+ CriticalPathMI = CriticalPathSU->getInstr();
+ } else {
+ // We've reached the end of the critical path.
+ CriticalPathSU = 0;
+ CriticalPathMI = 0;
+ }
+ }
// Scan the register operands for this instruction and update
// Classes and RegRefs.
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
const TargetRegisterClass *NewRC =
- getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
+ getInstrOperandRegClass(TRI, MI->getDesc(), i);
// If this instruction has a use of AntiDepReg, breaking it
// is invalid.
// TODO: Instead of picking the first free register, consider which might
// be the best.
if (AntiDepReg != 0) {
- for (TargetRegisterClass::iterator R = RC->allocation_order_begin(*MF),
- RE = RC->allocation_order_end(*MF); R != RE; ++R) {
+ for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
+ RE = RC->allocation_order_end(MF); R != RE; ++R) {
unsigned NewReg = *R;
// Don't replace a register with itself.
if (NewReg == AntiDepReg) continue;
if (NewReg == LastNewReg[AntiDepReg]) continue;
// If NewReg is dead and NewReg's most recent def is not before
// AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
- assert(((KillIndices[AntiDepReg] == -1u) != (DefIndices[AntiDepReg] == -1u)) &&
+ assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) &&
"Kill and Def maps aren't consistent for AntiDepReg!");
- assert(((KillIndices[NewReg] == -1u) != (DefIndices[NewReg] == -1u)) &&
+ assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) &&
"Kill and Def maps aren't consistent for NewReg!");
- if (KillIndices[NewReg] == -1u &&
+ if (KillIndices[NewReg] == ~0u &&
Classes[NewReg] != reinterpret_cast<TargetRegisterClass *>(-1) &&
KillIndices[AntiDepReg] <= DefIndices[NewReg]) {
DOUT << "Breaking anti-dependence edge on "
Classes[AntiDepReg] = 0;
DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
- KillIndices[AntiDepReg] = -1;
+ KillIndices[AntiDepReg] = ~0u;
RegRefs.erase(AntiDepReg);
Changed = true;
if (MI->isRegReDefinedByTwoAddr(i)) continue;
DefIndices[Reg] = Count;
- KillIndices[Reg] = -1;
+ KillIndices[Reg] = ~0u;
Classes[Reg] = 0;
RegRefs.erase(Reg);
// Repeat, for all subregs.
*Subreg; ++Subreg) {
unsigned SubregReg = *Subreg;
DefIndices[SubregReg] = Count;
- KillIndices[SubregReg] = -1;
+ KillIndices[SubregReg] = ~0u;
Classes[SubregReg] = 0;
RegRefs.erase(SubregReg);
}
+ // Conservatively mark super-registers as unusable.
for (const unsigned *Super = TRI->getSuperRegisters(Reg);
*Super; ++Super) {
unsigned SuperReg = *Super;
if (!MO.isUse()) continue;
const TargetRegisterClass *NewRC =
- getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
+ getInstrOperandRegClass(TRI, MI->getDesc(), i);
// For now, only allow the register to be changed if its register
// class is consistent across all uses.
RegRefs.insert(std::make_pair(Reg, &MO));
// It wasn't previously live but now it is, this is a kill.
- if (KillIndices[Reg] == -1u) {
+ if (KillIndices[Reg] == ~0u) {
KillIndices[Reg] = Count;
- DefIndices[Reg] = -1u;
+ DefIndices[Reg] = ~0u;
}
// Repeat, for all aliases.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
- if (KillIndices[AliasReg] == -1u) {
+ if (KillIndices[AliasReg] == ~0u) {
KillIndices[AliasReg] = Count;
- DefIndices[AliasReg] = -1u;
+ DefIndices[AliasReg] = ~0u;
}
}
}
}
- assert(Count == -1u && "Count mismatch!");
+ assert(Count == ~0u && "Count mismatch!");
return Changed;
}
// While Available queue is not empty, grab the node with the highest
// priority. If it is not ready put it back. Schedule the node.
+ std::vector<SUnit*> NotReady;
Sequence.reserve(SUnits.size());
while (!AvailableQueue.empty() || !PendingQueue.empty()) {
// Check to see if any of the pending instructions are ready to issue. If
MinDepth = PendingQueue[i]->getDepth();
}
- // If there are no instructions available, don't try to issue anything.
+ // If there are no instructions available, don't try to issue anything, and
+ // don't advance the hazard recognizer.
if (AvailableQueue.empty()) {
CurCycle = MinDepth != ~0u ? MinDepth : CurCycle + 1;
continue;
}
- SUnit *FoundSUnit = AvailableQueue.pop();
-
+ SUnit *FoundSUnit = 0;
+
+ bool HasNoopHazards = false;
+ while (!AvailableQueue.empty()) {
+ SUnit *CurSUnit = AvailableQueue.pop();
+
+ ScheduleHazardRecognizer::HazardType HT =
+ HazardRec->getHazardType(CurSUnit);
+ if (HT == ScheduleHazardRecognizer::NoHazard) {
+ FoundSUnit = CurSUnit;
+ break;
+ }
+
+ // Remember if this is a noop hazard.
+ HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
+
+ NotReady.push_back(CurSUnit);
+ }
+
+ // Add the nodes that aren't ready back onto the available list.
+ if (!NotReady.empty()) {
+ AvailableQueue.push_all(NotReady);
+ NotReady.clear();
+ }
+
// If we found a node to schedule, do it now.
if (FoundSUnit) {
ScheduleNodeTopDown(FoundSUnit, CurCycle);
+ HazardRec->EmitInstruction(FoundSUnit);
// If this is a pseudo-op node, we don't want to increment the current
// cycle.
if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
- ++CurCycle;
- } else {
+ ++CurCycle;
+ } else if (!HasNoopHazards) {
// Otherwise, we have a pipeline stall, but no other problem, just advance
// the current cycle and try again.
DOUT << "*** Advancing cycle, no work to do\n";
+ HazardRec->AdvanceCycle();
++NumStalls;
++CurCycle;
+ } else {
+ // Otherwise, we have no instructions to issue and we have instructions
+ // that will fault if we don't do this right. This is the case for
+ // processors without pipeline interlocks and other cases.
+ DOUT << "*** Emitting noop\n";
+ HazardRec->EmitNoop();
+ Sequence.push_back(0); // NULL here means noop
+ ++NumNoops;
+ ++CurCycle;
}
}
projects / oota-llvm.git / blobdiff