Remove extraneous close parenthesis.

[oota-llvm.git] / lib / CodeGen / RegAllocGreedy.cpp

diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index e88016fbb374957feb4d08715d49fb3e48c674fd..af2c55e7d89cf03f6b3d8c03e888ca4650345721 100644 (file)
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -232,7 +232,7 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
   // Check for an available register in this class.
   DEBUG({
       const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
-      dbgs() << "RegClass: " << TRC->getName() << ' ');
+      dbgs() << "RegClass: " << TRC->getName() << ' ';
     });
 
   AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);