unsigned reg = i->reg;
// remove expired intervals
- if (i->expiredAt(cur->start())) {
+ if (i->expiredAt(cur->beginNumber())) {
DEBUG(std::cerr << "\t\tinterval " << *i << " expired\n");
if (MRegisterInfo::isVirtualRegister(reg))
reg = vrm_->getPhys(reg);
std::iter_swap(ii, --ie);
}
// move inactive intervals to inactive list
- else if (!i->liveAt(cur->start())) {
+ else if (!i->liveAt(cur->beginNumber())) {
DEBUG(std::cerr << "\t\tinterval " << *i << " inactive\n");
if (MRegisterInfo::isVirtualRegister(reg))
reg = vrm_->getPhys(reg);
unsigned reg = i->reg;
// remove expired intervals
- if (i->expiredAt(cur->start())) {
+ if (i->expiredAt(cur->beginNumber())) {
DEBUG(std::cerr << "\t\tinterval " << *i << " expired\n");
// swap with last element and move end iterator back one position
std::iter_swap(ii, --ie);
}
// move re-activated intervals in active list
- else if (i->liveAt(cur->start())) {
+ else if (i->liveAt(cur->beginNumber())) {
DEBUG(std::cerr << "\t\tinterval " << *i << " active\n");
if (MRegisterInfo::isVirtualRegister(reg))
reg = vrm_->getPhys(reg);
DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n");
- float minWeight = HUGE_VAL;
+ float minWeight = (float)HUGE_VAL;
unsigned minReg = 0;
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
- for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
- i != rc->allocation_order_end(*mf_); ++i) {
+ for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_),
+ e = rc->allocation_order_end(*mf_); i != e; ++i) {
unsigned reg = *i;
if (minWeight > spillWeights_[reg]) {
minWeight = spillWeights_[reg];
toSpill[minReg] = true;
for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as)
toSpill[*as] = true;
- unsigned earliestStart = cur->start();
+ unsigned earliestStart = cur->beginNumber();
std::set<unsigned> spilled;
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
unsigned freeReg = 0;
- for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
- i != rc->allocation_order_end(*mf_); ++i) {
+ for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_),
+ e = rc->allocation_order_end(*mf_); i != e; ++i) {
unsigned reg = *i;
if (prt_->isRegAvail(reg) &&
(!freeReg || inactiveCounts[freeReg] < inactiveCounts[reg]))