Revamp supported ops. Instead of just being supported or not, we now keep

[oota-llvm.git] / lib / CodeGen / RegAllocLinearScan.cpp

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index c54152a1492eda026b04fa52f1918ba564426f08..0878e466d23473a7faf882212bc5d734dd9379ec 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -423,11 +423,11 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
 
   DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n");
 
-  float minWeight = HUGE_VAL;
+  float minWeight = float(HUGE_VAL);
   unsigned minReg = 0;
   const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
-  for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
-       i != rc->allocation_order_end(*mf_); ++i) {
+  for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_),
+       e = rc->allocation_order_end(*mf_); i != e; ++i) {
     unsigned reg = *i;
     if (minWeight > SpillWeights[reg]) {
       minWeight = SpillWeights[reg];
@@ -608,8 +608,8 @@ unsigned RA::getFreePhysReg(LiveInterval* cur)
   const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
 
   unsigned freeReg = 0;
-  for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
-       i != rc->allocation_order_end(*mf_); ++i) {
+  for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_),
+       e = rc->allocation_order_end(*mf_); i != e; ++i) {
     unsigned reg = *i;
     if (prt_->isRegAvail(reg) &&
         (!freeReg || inactiveCounts[freeReg] < inactiveCounts[reg]))