++NumIters;
DOUT << "\n*** CURRENT ***: " << *cur << '\n';
- processActiveIntervals(cur->beginNumber());
- processInactiveIntervals(cur->beginNumber());
+ if (!cur->empty()) {
+ processActiveIntervals(cur->beginNumber());
+ processInactiveIntervals(cur->beginNumber());
- assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
- "Can only allocate virtual registers!");
+ assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
+ "Can only allocate virtual registers!");
+ }
// Allocating a virtual register. try to find a free
// physical register or spill an interval (possibly this one) in order to
{
DOUT << "\tallocating current interval: ";
+ // This is an implicitly defined live interval, just assign any register.
+ const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
+ if (cur->empty()) {
+ unsigned physReg = cur->preference;
+ if (!physReg)
+ physReg = *RC->allocation_order_begin(*mf_);
+ DOUT << tri_->getName(physReg) << '\n';
+ // Note the register is not really in use.
+ vrm_->assignVirt2Phys(cur->reg, physReg);
+ return;
+ }
+
PhysRegTracker backupPrt = *prt_;
std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
unsigned StartPosition = cur->beginNumber();
- const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
// If this live interval is defined by a move instruction and its source is
if (vni->def && vni->def != ~1U && vni->def != ~0U) {
MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
unsigned SrcReg, DstReg;
- if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
+ if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
unsigned Reg = 0;
if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
Reg = SrcReg;
// All registers must have inf weight. Just grab one!
if (!minReg) {
- if (BestPhysReg)
- minReg = BestPhysReg;
- else {
- // Get the physical register with the fewest conflicts.
- unsigned MinConflicts = ~0U;
- for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
- e = RC->allocation_order_end(*mf_); i != e; ++i) {
- unsigned reg = *i;
- unsigned NumConflicts = li_->getNumConflictsWithPhysReg(*cur, reg);
- if (NumConflicts <= MinConflicts) {
- MinConflicts = NumConflicts;
- minReg = reg;
- }
- }
- }
-
- if (cur->weight == HUGE_VALF || cur->getSize() == 1)
- // Spill a physical register around defs and uses.
- li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
+ minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
+ if (cur->weight == HUGE_VALF || cur->getSize() == 1)
+ // Spill a physical register around defs and uses.
+ li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
}
}
// Scan for the first available register.
TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
+ assert(I != E && "No allocatable register in this register class!");
for (; I != E; ++I)
if (prt_->isRegAvail(*I)) {
FreeReg = *I;