Fix spellnig error

[oota-llvm.git] / lib / CodeGen / RegAllocLinearScan.cpp

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index d43cc19683c4a4be86b823f2e0c7416ca1e4d26e..456ee6319c146cf1ea21c9cb36cec266fa3d10f9 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -322,11 +322,13 @@ void RALinScan::linearScan()
     ++NumIters;
     DOUT << "\n*** CURRENT ***: " << *cur << '\n';
 
-    processActiveIntervals(cur->beginNumber());
-    processInactiveIntervals(cur->beginNumber());
+    if (!cur->empty()) {
+      processActiveIntervals(cur->beginNumber());
+      processInactiveIntervals(cur->beginNumber());
 
-    assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
-           "Can only allocate virtual registers!");
+      assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
+             "Can only allocate virtual registers!");
+    }
 
     // Allocating a virtual register. try to find a free
     // physical register or spill an interval (possibly this one) in order to
@@ -508,11 +510,22 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
 {
   DOUT << "\tallocating current interval: ";
 
+  // This is an implicitly defined live interval, just assign any register.
+  const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
+  if (cur->empty()) {
+    unsigned physReg = cur->preference;
+    if (!physReg)
+      physReg = *RC->allocation_order_begin(*mf_);
+    DOUT <<  tri_->getName(physReg) << '\n';
+    // Note the register is not really in use.
+    vrm_->assignVirt2Phys(cur->reg, physReg);
+    return;
+  }
+
   PhysRegTracker backupPrt = *prt_;
 
   std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
   unsigned StartPosition = cur->beginNumber();
-  const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
   const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
 
   // If this live interval is defined by a move instruction and its source is
@@ -525,7 +538,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
     if (vni->def && vni->def != ~1U && vni->def != ~0U) {
       MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
       unsigned SrcReg, DstReg;
-      if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
+      if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
         unsigned Reg = 0;
         if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
           Reg = SrcReg;
@@ -561,6 +574,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   // is very bad (it contains all callee clobbered registers for any functions
   // with a call), so we want to avoid doing that if possible.
   unsigned physReg = getFreePhysReg(cur);
+  unsigned BestPhysReg = physReg;
   if (physReg) {
     // We got a register.  However, if it's in the fixed_ list, we might
     // conflict with it.  Check to see if we conflict with it or any of its
@@ -685,8 +699,12 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
     }
 
     // All registers must have inf weight. Just grab one!
-    if (!minReg)
-      minReg = *RC->allocation_order_begin(*mf_);
+    if (!minReg) {
+        minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
+        if (cur->weight == HUGE_VALF || cur->getSize() == 1)
+          // Spill a physical register around defs and uses.
+          li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
+    }
   }
   
   DOUT << "\t\tregister with min weight: "
@@ -881,6 +899,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   // Scan for the first available register.
   TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
   TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
+  assert(I != E && "No allocatable register in this register class!");
   for (; I != E; ++I)
     if (prt_->isRegAvail(*I)) {
       FreeReg = *I;