#include "VirtRegRewriter.h"
#include "Spiller.h"
#include "llvm/Function.h"
+#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
cl::desc("Pre-register allocation live interval splitting"),
cl::init(false), cl::Hidden);
+static cl::opt<bool>
+TrivCoalesceEnds("trivial-coalesce-ends",
+ cl::desc("Attempt trivial coalescing of interval ends"),
+ cl::init(false), cl::Hidden);
+
static RegisterRegAlloc
linearscanRegAlloc("linearscan", "linear scan register allocator",
createLinearScanRegisterAllocator);
// Make sure PassManager knows which analyses to make available
// to coalescing and which analyses coalescing invalidates.
AU.addRequiredTransitive<RegisterCoalescer>();
+ AU.addRequired<CalculateSpillWeights>();
if (PreSplitIntervals)
AU.addRequiredID(PreAllocSplittingID);
AU.addRequired<LiveStacks>();
bool Error = false;
for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
if (regUse_[i] != 0) {
- errs() << tri_->getName(i) << " is still in use!\n";
+ dbgs() << tri_->getName(i) << " is still in use!\n";
Error = true;
}
}
SmallVector<unsigned, 256> &inactiveCounts,
bool SkipDGRegs);
- /// assignVirt2StackSlot - assigns this virtual register to a
- /// stack slot. returns the stack slot
- int assignVirt2StackSlot(unsigned virtReg);
-
void ComputeRelatedRegClasses();
template <typename ItTy>
void printIntervals(const char* const str, ItTy i, ItTy e) const {
DEBUG({
if (str)
- errs() << str << " intervals:\n";
+ dbgs() << str << " intervals:\n";
for (; i != e; ++i) {
- errs() << "\t" << *i->first << " -> ";
+ dbgs() << "\t" << *i->first << " -> ";
unsigned reg = i->first->reg;
if (TargetRegisterInfo::isVirtualRegister(reg))
reg = vrm_->getPhys(reg);
- errs() << tri_->getName(reg) << '\n';
+ dbgs() << tri_->getName(reg) << '\n';
}
});
}
RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
}
-/// attemptTrivialCoalescing - If a simple interval is defined by a copy,
-/// try allocate the definition the same register as the source register
-/// if the register is not defined during live time of the interval. This
-/// eliminate a copy. This is used to coalesce copies which were not
-/// coalesced away before allocation either due to dest and src being in
-/// different register classes or because the coalescer was overly
-/// conservative.
+/// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
+/// allocate the definition the same register as the source register if the
+/// register is not defined during live time of the interval. If the interval is
+/// killed by a copy, try to use the destination register. This eliminates a
+/// copy. This is used to coalesce copies which were not coalesced away before
+/// allocation either due to dest and src being in different register classes or
+/// because the coalescer was overly conservative.
unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
unsigned Preference = vrm_->getRegAllocPref(cur.reg);
if ((Preference && Preference == Reg) || !cur.containsOneValue())
return Reg;
- VNInfo *vni = cur.begin()->valno;
- if ((vni->def == SlotIndex()) ||
- vni->isUnused() || !vni->isDefAccurate())
+ // We cannot handle complicated live ranges. Simple linear stuff only.
+ if (cur.ranges.size() != 1)
return Reg;
- MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
- if (!CopyMI ||
- !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
+
+ const LiveRange &range = cur.ranges.front();
+
+ VNInfo *vni = range.valno;
+ if (vni->isUnused())
return Reg;
- PhysReg = SrcReg;
- if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
- if (!vrm_->isAssignedReg(SrcReg))
+
+ unsigned CandReg;
+ {
+ MachineInstr *CopyMI;
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+ if (vni->def != SlotIndex() && vni->isDefAccurate() &&
+ (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
+ tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
+ // Defined by a copy, try to extend SrcReg forward
+ CandReg = SrcReg;
+ else if (TrivCoalesceEnds &&
+ (CopyMI =
+ li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
+ tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
+ cur.reg == SrcReg)
+ // Only used by a copy, try to extend DstReg backwards
+ CandReg = DstReg;
+ else
+ return Reg;
+ }
+
+ if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
+ if (!vrm_->isAssignedReg(CandReg))
return Reg;
- PhysReg = vrm_->getPhys(SrcReg);
+ CandReg = vrm_->getPhys(CandReg);
}
- if (Reg == PhysReg)
+ if (Reg == CandReg)
return Reg;
const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
- if (!RC->contains(PhysReg))
+ if (!RC->contains(CandReg))
return Reg;
- // Try to coalesce.
- if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
- DEBUG(errs() << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
- << '\n');
- vrm_->clearVirt(cur.reg);
- vrm_->assignVirt2Phys(cur.reg, PhysReg);
-
- // Remove unnecessary kills since a copy does not clobber the register.
- if (li_->hasInterval(SrcReg)) {
- LiveInterval &SrcLI = li_->getInterval(SrcReg);
- for (MachineRegisterInfo::use_iterator I = mri_->use_begin(cur.reg),
- E = mri_->use_end(); I != E; ++I) {
- MachineOperand &O = I.getOperand();
- if (!O.isKill())
- continue;
- MachineInstr *MI = &*I;
- if (SrcLI.liveAt(li_->getInstructionIndex(MI).getDefIndex()))
- O.setIsKill(false);
- }
- }
+ if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
+ return Reg;
- ++NumCoalesce;
- return PhysReg;
- }
+ // Try to coalesce.
+ DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
+ << '\n');
+ vrm_->clearVirt(cur.reg);
+ vrm_->assignVirt2Phys(cur.reg, CandReg);
- return Reg;
+ ++NumCoalesce;
+ return CandReg;
}
bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
void RALinScan::linearScan() {
// linear scan algorithm
DEBUG({
- errs() << "********** LINEAR SCAN **********\n"
+ dbgs() << "********** LINEAR SCAN **********\n"
<< "********** Function: "
<< mf_->getFunction()->getName() << '\n';
printIntervals("fixed", fixed_.begin(), fixed_.end());
LiveInterval* cur = unhandled_.top();
unhandled_.pop();
++NumIters;
- DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
+ DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
assert(!cur->empty() && "Empty interval in unhandled set.");
while (!active_.empty()) {
IntervalPtr &IP = active_.back();
unsigned reg = IP.first->reg;
- DEBUG(errs() << "\tinterval " << *IP.first << " expired\n");
+ DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
DEBUG({
for (IntervalPtrs::reverse_iterator
i = inactive_.rbegin(); i != inactive_.rend(); ++i)
- errs() << "\tinterval " << *i->first << " expired\n";
+ dbgs() << "\tinterval " << *i->first << " expired\n";
});
inactive_.clear();
}
}
- DEBUG(errs() << *vrm_);
+ DEBUG(dbgs() << *vrm_);
// Look for physical registers that end up not being allocated even though
// register allocator had to spill other registers in its register class.
/// to the inactive list.
void RALinScan::processActiveIntervals(SlotIndex CurPoint)
{
- DEBUG(errs() << "\tprocessing active intervals:\n");
+ DEBUG(dbgs() << "\tprocessing active intervals:\n");
for (unsigned i = 0, e = active_.size(); i != e; ++i) {
LiveInterval *Interval = active_[i].first;
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
if (IntervalPos == Interval->end()) { // Remove expired intervals.
- DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
+ DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
} else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list.
- DEBUG(errs() << "\t\tinterval " << *Interval << " inactive\n");
+ DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
/// ones to the active list.
void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
{
- DEBUG(errs() << "\tprocessing inactive intervals:\n");
+ DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
LiveInterval *Interval = inactive_[i].first;
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
if (IntervalPos == Interval->end()) { // remove expired intervals.
- DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
+ DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
// Pop off the end of the list.
inactive_[i] = inactive_.back();
--i; --e;
} else if (IntervalPos->start <= CurPoint) {
// move re-activated intervals in active list
- DEBUG(errs() << "\t\tinterval " << *Interval << " active\n");
+ DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
SmallVector<LiveInterval*, 8> SLIs[3];
DEBUG({
- errs() << "\tConsidering " << NumCands << " candidates: ";
+ dbgs() << "\tConsidering " << NumCands << " candidates: ";
for (unsigned i = 0; i != NumCands; ++i)
- errs() << tri_->getName(Candidates[i].first) << " ";
- errs() << "\n";
+ dbgs() << tri_->getName(Candidates[i].first) << " ";
+ dbgs() << "\n";
});
// Calculate the number of conflicts of each candidate.
const RALinScan &Allocator;
public:
- WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {};
+ WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
typedef std::pair<unsigned, float> RegWeightPair;
bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
/// spill.
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
- DEBUG(errs() << "\tallocating current interval: ");
+ DEBUG(dbgs() << "\tallocating current interval: ");
// This is an implicitly defined live interval, just assign any register.
const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
unsigned physReg = vrm_->getRegAllocPref(cur->reg);
if (!physReg)
physReg = *RC->allocation_order_begin(*mf_);
- DEBUG(errs() << tri_->getName(physReg) << '\n');
+ DEBUG(dbgs() << tri_->getName(physReg) << '\n');
// Note the register is not really in use.
vrm_->assignVirt2Phys(cur->reg, physReg);
return;
// the free physical register and add this interval to the active
// list.
if (physReg) {
- DEBUG(errs() << tri_->getName(physReg) << '\n');
+ DEBUG(dbgs() << tri_->getName(physReg) << '\n');
vrm_->assignVirt2Phys(cur->reg, physReg);
addRegUse(physReg);
active_.push_back(std::make_pair(cur, cur->begin()));
}
return;
}
- DEBUG(errs() << "no free registers\n");
+ DEBUG(dbgs() << "no free registers\n");
// Compile the spill weights into an array that is better for scanning.
std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
}
- DEBUG(errs() << "\tassigning stack slot at interval "<< *cur << ":\n");
+ DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
// Find a register to spill.
float minWeight = HUGE_VALF;
assignRegOrStackSlotAtInterval(cur);
} else {
assert(false && "Ran out of registers during register allocation!");
- llvm_report_error("Ran out of registers during register allocation!");
+ report_fatal_error("Ran out of registers during register allocation!");
}
return;
}
}
DEBUG({
- errs() << "\t\tregister(s) with min weight(s): ";
+ dbgs() << "\t\tregister(s) with min weight(s): ";
for (unsigned i = 0; i != LastCandidate; ++i)
- errs() << tri_->getName(RegsWeights[i].first)
+ dbgs() << tri_->getName(RegsWeights[i].first)
<< " (" << RegsWeights[i].second << ")\n";
});
// add any added intervals back to unhandled, and restart
// linearscan.
if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
- DEBUG(errs() << "\t\t\tspilling(c): " << *cur << '\n');
+ DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
SmallVector<LiveInterval*, 8> spillIs;
std::vector<LiveInterval*> added;
// The earliest start of a Spilled interval indicates up to where
// in handled we need to roll back
+ assert(!spillIs.empty() && "No spill intervals?");
+ SlotIndex earliestStart = spillIs[0]->beginIndex();
- LiveInterval *earliestStartInterval = cur;
-
// Spill live intervals of virtual regs mapped to the physical register we
// want to clear (and its aliases). We only spill those that overlap with the
// current interval as the rest do not affect its allocation. we also keep
while (!spillIs.empty()) {
LiveInterval *sli = spillIs.back();
spillIs.pop_back();
- DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
- earliestStartInterval =
- (earliestStartInterval->beginIndex() < sli->beginIndex()) ?
- earliestStartInterval : sli;
+ DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
+ if (sli->beginIndex() < earliestStart)
+ earliestStart = sli->beginIndex();
std::vector<LiveInterval*> newIs;
- newIs = spiller_->spill(sli, spillIs);
+ newIs = spiller_->spill(sli, spillIs, &earliestStart);
addStackInterval(sli, ls_, li_, mri_, *vrm_);
std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
spilled.insert(sli->reg);
}
- SlotIndex earliestStart = earliestStartInterval->beginIndex();
-
- DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
+ DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
// Scan handled in reverse order up to the earliest start of a
// spilled live interval and undo each one, restoring the state of
while (!handled_.empty()) {
LiveInterval* i = handled_.back();
// If this interval starts before t we are done.
- if (i->beginIndex() < earliestStart)
+ if (!i->empty() && i->beginIndex() < earliestStart)
break;
- DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
+ DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
handled_.pop_back();
// When undoing a live interval allocation we must know if it is active or
LiveInterval *HI = handled_[i];
if (!HI->expiredAt(earliestStart) &&
HI->expiredAt(cur->beginIndex())) {
- DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
+ DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
active_.push_back(std::make_pair(HI, HI->begin()));
assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
addRegUse(vrm_->getPhys(HI->reg));
// available first.
unsigned Preference = vrm_->getRegAllocPref(cur->reg);
if (Preference) {
- DEBUG(errs() << "(preferred: " << tri_->getName(Preference) << ") ");
+ DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
if (isRegAvail(Preference) &&
RC->contains(Preference))
return Preference;
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