Fold trivial two-operand tokenfactors where the operands are equal

[oota-llvm.git] / lib / CodeGen / RegAllocLinearScan.cpp

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 0279db6ab17725aeb2c3f456039678018487d45e..7291e12bbea438135a0ca0b7e0a9e7440f68c7ad 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -852,9 +852,12 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
     // All registers must have inf weight. Just grab one!
     minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
     if (cur->weight == HUGE_VALF ||
-        li_->getApproximateInstructionCount(*cur) == 0)
+        li_->getApproximateInstructionCount(*cur) == 0) {
       // Spill a physical register around defs and uses.
       li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
+      assignRegOrStackSlotAtInterval(cur);
+      return;
+    }
   }
 
   // Find up to 3 registers to consider as spill candidates.
@@ -876,8 +879,9 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
     DOUT << "\t\t\tspilling(c): " << *cur << '\n';
     float SSWeight;
+    SmallVector<LiveInterval*, 8> spillIs;
     std::vector<LiveInterval*> added =
-      li_->addIntervalsForSpills(*cur, loopInfo, *vrm_, SSWeight);
+      li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_, SSWeight);
     addStackInterval(cur, ls_, li_, SSWeight, *vrm_);
     if (added.empty())
       return;  // Early exit if all spills were folded.
@@ -928,7 +932,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
     earliestStart = std::min(earliestStart, sli->beginNumber());
     float SSWeight;
     std::vector<LiveInterval*> newIs =
-      li_->addIntervalsForSpills(*sli, loopInfo, *vrm_, SSWeight);
+      li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_, SSWeight);
     addStackInterval(sli, ls_, li_, SSWeight, *vrm_);
     std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
     spilled.insert(sli->reg);
@@ -1034,7 +1038,8 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   // If copy coalescer has assigned a "preferred" register, check if it's
   // available first.
   if (cur->preference) {
-    if (prt_->isRegAvail(cur->preference) && RC->contains(cur->preference)) {
+    if (prt_->isRegAvail(cur->preference) && 
+        RC->contains(cur->preference)) {
       DOUT << "\t\tassigned the preferred register: "
            << tri_->getName(cur->preference) << "\n";
       return cur->preference;
@@ -1048,8 +1053,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
   assert(I != E && "No allocatable register in this register class!");
   for (; I != E; ++I)
-    if (prt_->isRegAvail(*I) && 
-        li_->noEarlyclobberConflict(cur->reg, *vrm_, *I)) {
+    if (prt_->isRegAvail(*I)) {
       FreeReg = *I;
       if (FreeReg < inactiveCounts.size())
         FreeRegInactiveCount = inactiveCounts[FreeReg];
@@ -1069,8 +1073,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   for (; I != E; ++I) {
     unsigned Reg = *I;
     if (prt_->isRegAvail(Reg) && Reg < inactiveCounts.size() &&
-        FreeRegInactiveCount < inactiveCounts[Reg] &&
-        li_->noEarlyclobberConflict(cur->reg, *vrm_, Reg)) {
+        FreeRegInactiveCount < inactiveCounts[Reg]) {
       FreeReg = Reg;
       FreeRegInactiveCount = inactiveCounts[Reg];
       if (FreeRegInactiveCount == MaxInactiveCount)