Fold trivial two-operand tokenfactors where the operands are equal

[oota-llvm.git] / lib / CodeGen / RegAllocLinearScan.cpp

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index a26924be6279a3350bfecd10d38b3702bf2180dc..7291e12bbea438135a0ca0b7e0a9e7440f68c7ad 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -55,23 +55,22 @@ linearscanRegAlloc("linearscan", "  linear scan register allocator",
 namespace {
   struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
     static char ID;
-    RALinScan() : MachineFunctionPass((intptr_t)&ID) {}
+    RALinScan() : MachineFunctionPass(&ID) {}
 
     typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
-    typedef std::vector<IntervalPtr> IntervalPtrs;
+    typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
   private:
     /// RelatedRegClasses - This structure is built the first time a function is
     /// compiled, and keeps track of which register classes have registers that
     /// belong to multiple classes or have aliases that are in other classes.
     EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
-    std::map<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
+    DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
 
     MachineFunction* mf_;
     MachineRegisterInfo* mri_;
     const TargetMachine* tm_;
     const TargetRegisterInfo* tri_;
     const TargetInstrInfo* tii_;
-    MachineRegisterInfo *reginfo_;
     BitVector allocatableRegs_;
     LiveIntervals* li_;
     LiveStacks* ls_;
@@ -94,7 +93,7 @@ namespace {
     IntervalPtrs inactive_;
 
     typedef std::priority_queue<LiveInterval*,
-                                std::vector<LiveInterval*>,
+                                SmallVector<LiveInterval*, 64>,
                                 greater_ptr<LiveInterval> > IntervalHeap;
     IntervalHeap unhandled_;
     std::auto_ptr<PhysRegTracker> prt_;
@@ -221,7 +220,7 @@ void RALinScan::ComputeRelatedRegClasses() {
   // belongs to, add info about aliases.  We don't need to do this for targets
   // without register aliases.
   if (HasAliases)
-    for (std::map<unsigned, const TargetRegisterClass*>::iterator
+    for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
          I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
          I != E; ++I)
       for (const unsigned *AS = TRI.getAliasSet(I->first); *AS; ++AS)
@@ -255,7 +254,7 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
   if (Reg == SrcReg)
     return Reg;
 
-  const TargetRegisterClass *RC = reginfo_->getRegClass(cur.reg);
+  const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
   if (!RC->contains(SrcReg))
     return Reg;
 
@@ -278,7 +277,6 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
   tm_ = &fn.getTarget();
   tri_ = tm_->getRegisterInfo();
   tii_ = tm_->getInstrInfo();
-  reginfo_ = &mf_->getRegInfo();
   allocatableRegs_ = tri_->getAllocatableSet(fn);
   li_ = &getAnalysis<LiveIntervals>();
   ls_ = &getAnalysis<LiveStacks>();
@@ -322,12 +320,14 @@ void RALinScan::initIntervalSets()
          active_.empty() && inactive_.empty() &&
          "interval sets should be empty on initialization");
 
+  handled_.reserve(li_->getNumIntervals());
+
   for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
-    if (TargetRegisterInfo::isPhysicalRegister(i->second.reg)) {
-      reginfo_->setPhysRegUsed(i->second.reg);
-      fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
+    if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
+      mri_->setPhysRegUsed(i->second->reg);
+      fixed_.push_back(std::make_pair(i->second, i->second->begin()));
     } else
-      unhandled_.push(&i->second);
+      unhandled_.push(i->second);
   }
 }
 
@@ -385,11 +385,11 @@ void RALinScan::linearScan()
   MachineFunction::iterator EntryMBB = mf_->begin();
   SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
   for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
-    LiveInterval &cur = i->second;
+    LiveInterval &cur = *i->second;
     unsigned Reg = 0;
     bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
     if (isPhys)
-      Reg = i->second.reg;
+      Reg = cur.reg;
     else if (vrm_->isAssignedReg(cur.reg))
       Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
     if (!Reg)
@@ -658,7 +658,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   DOUT << "\tallocating current interval: ";
 
   // This is an implicitly defined live interval, just assign any register.
-  const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
+  const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
   if (cur->empty()) {
     unsigned physReg = cur->preference;
     if (!physReg)
@@ -704,7 +704,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
     unsigned Reg = i->first->reg;
     assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
            "Can only allocate virtual registers!");
-    const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg);
+    const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
     // If this is not in a related reg class to the register we're allocating, 
     // don't check it.
     if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
@@ -851,9 +851,13 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   if (minWeight == HUGE_VALF) {
     // All registers must have inf weight. Just grab one!
     minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
-    if (cur->weight == HUGE_VALF || cur->getSize() == 1)
+    if (cur->weight == HUGE_VALF ||
+        li_->getApproximateInstructionCount(*cur) == 0) {
       // Spill a physical register around defs and uses.
       li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
+      assignRegOrStackSlotAtInterval(cur);
+      return;
+    }
   }
 
   // Find up to 3 registers to consider as spill candidates.
@@ -875,8 +879,9 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
     DOUT << "\t\t\tspilling(c): " << *cur << '\n';
     float SSWeight;
+    SmallVector<LiveInterval*, 8> spillIs;
     std::vector<LiveInterval*> added =
-      li_->addIntervalsForSpills(*cur, loopInfo, *vrm_, SSWeight);
+      li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_, SSWeight);
     addStackInterval(cur, ls_, li_, SSWeight, *vrm_);
     if (added.empty())
       return;  // Early exit if all spills were folded.
@@ -927,7 +932,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
     earliestStart = std::min(earliestStart, sli->beginNumber());
     float SSWeight;
     std::vector<LiveInterval*> newIs =
-      li_->addIntervalsForSpills(*sli, loopInfo, *vrm_, SSWeight);
+      li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_, SSWeight);
     addStackInterval(sli, ls_, li_, SSWeight, *vrm_);
     std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
     spilled.insert(sli->reg);
@@ -1006,7 +1011,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   SmallVector<unsigned, 256> inactiveCounts;
   unsigned MaxInactiveCount = 0;
   
-  const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
+  const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
   const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
  
   for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
@@ -1017,7 +1022,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
 
     // If this is not in a related reg class to the register we're allocating, 
     // don't check it.
-    const TargetRegisterClass *RegRC = reginfo_->getRegClass(reg);
+    const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
     if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
       reg = vrm_->getPhys(reg);
       if (inactiveCounts.size() <= reg)
@@ -1033,7 +1038,8 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   // If copy coalescer has assigned a "preferred" register, check if it's
   // available first.
   if (cur->preference) {
-    if (prt_->isRegAvail(cur->preference)) {
+    if (prt_->isRegAvail(cur->preference) && 
+        RC->contains(cur->preference)) {
       DOUT << "\t\tassigned the preferred register: "
            << tri_->getName(cur->preference) << "\n";
       return cur->preference;