refactor some code, no functionality change

[oota-llvm.git] / lib / CodeGen / RegAllocLinearScan.cpp

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 76fc5809f528f16fba0b1b0e4ab7c69867fb4105..8ad347bb7dad15fa90e7c4a2141b701e4dfd96dd 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "regalloc"
+#include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
 #include "PhysRegTracker.h"
 #include "VirtRegMap.h"
@@ -60,7 +61,6 @@ namespace {
     const TargetMachine* tm_;
     const MRegisterInfo* mri_;
     LiveIntervals* li_;
-    bool *PhysRegsUsed;
 
     /// handled_ - Intervals are added to the handled_ set in the order of their
     /// start value.  This is uses for backtracking.
@@ -193,10 +193,6 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
   if (RelatedRegClasses.empty())
     ComputeRelatedRegClasses();
   
-  PhysRegsUsed = new bool[mri_->getNumRegs()];
-  std::fill(PhysRegsUsed, PhysRegsUsed+mri_->getNumRegs(), false);
-  fn.setUsedPhysRegs(PhysRegsUsed);
-
   if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_));
   vrm_.reset(new VirtRegMap(*mf_));
   if (!spiller_.get()) spiller_.reset(createSpiller());
@@ -230,7 +226,7 @@ void RA::initIntervalSets()
 
   for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
     if (MRegisterInfo::isPhysicalRegister(i->second.reg)) {
-      PhysRegsUsed[i->second.reg] = true;
+      mf_->setPhysRegUsed(i->second.reg);
       fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
     } else
       unhandled_.push(&i->second);
@@ -562,15 +558,17 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
 
   // Find a register to spill.
   float minWeight = HUGE_VALF;
-  unsigned minReg = 0;
-  for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
-       e = RC->allocation_order_end(*mf_); i != e; ++i) {
-    unsigned reg = *i;
-    if (minWeight > SpillWeights[reg]) {
-      minWeight = SpillWeights[reg];
-      minReg = reg;
+  unsigned minReg = cur->preference;  // Try the preferred register first.
+  
+  if (!minReg || SpillWeights[minReg] == HUGE_VALF)
+    for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
+           e = RC->allocation_order_end(*mf_); i != e; ++i) {
+      unsigned reg = *i;
+      if (minWeight > SpillWeights[reg]) {
+        minWeight = SpillWeights[reg];
+        minReg = reg;
+      }
     }
-  }
   
   // If we didn't find a register that is spillable, try aliases?
   if (!minReg) {
@@ -600,7 +598,12 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   // linearscan.
   if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
     DOUT << "\t\t\tspilling(c): " << *cur << '\n';
-    int slot = vrm_->assignVirt2StackSlot(cur->reg);
+    // if the current interval is re-materializable, remember so and don't
+    // assign it a spill slot.
+    if (cur->remat)
+      vrm_->setVirtIsReMaterialized(cur->reg, cur->remat);
+    int slot = cur->remat ? vrm_->assignVirtReMatId(cur->reg)
+      : vrm_->assignVirt2StackSlot(cur->reg);
     std::vector<LiveInterval*> added =
       li_->addIntervalsForSpills(*cur, *vrm_, slot);
     if (added.empty())
@@ -627,7 +630,7 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   std::vector<LiveInterval*> added;
   assert(MRegisterInfo::isPhysicalRegister(minReg) &&
          "did not choose a register to spill?");
-  std::vector<bool> toSpill(mri_->getNumRegs(), false);
+  BitVector toSpill(mri_->getNumRegs());
 
   // We are going to spill minReg and all its aliases.
   toSpill[minReg] = true;
@@ -653,7 +656,10 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
         cur->overlapsFrom(*i->first, i->second)) {
       DOUT << "\t\t\tspilling(a): " << *i->first << '\n';
       earliestStart = std::min(earliestStart, i->first->beginNumber());
-      int slot = vrm_->assignVirt2StackSlot(i->first->reg);
+      if (i->first->remat)
+        vrm_->setVirtIsReMaterialized(reg, i->first->remat);
+      int slot = i->first->remat ? vrm_->assignVirtReMatId(reg)
+        : vrm_->assignVirt2StackSlot(reg);
       std::vector<LiveInterval*> newIs =
         li_->addIntervalsForSpills(*i->first, *vrm_, slot);
       std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
@@ -667,7 +673,10 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
         cur->overlapsFrom(*i->first, i->second-1)) {
       DOUT << "\t\t\tspilling(i): " << *i->first << '\n';
       earliestStart = std::min(earliestStart, i->first->beginNumber());
-      int slot = vrm_->assignVirt2StackSlot(reg);
+      if (i->first->remat)
+        vrm_->setVirtIsReMaterialized(reg, i->first->remat);
+      int slot = i->first->remat ? vrm_->assignVirtReMatId(reg)
+        : vrm_->assignVirt2StackSlot(reg);
       std::vector<LiveInterval*> newIs =
         li_->addIntervalsForSpills(*i->first, *vrm_, slot);
       std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
@@ -762,14 +771,23 @@ unsigned RA::getFreePhysReg(LiveInterval *cur) {
     }
   }
 
-  const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
-
   unsigned FreeReg = 0;
   unsigned FreeRegInactiveCount = 0;
-  
+
+  // If copy coalescer has assigned a "preferred" register, check if it's
+  // available first.
+  if (cur->preference)
+    if (prt_->isRegAvail(cur->preference)) {
+      DOUT << "\t\tassigned the preferred register: "
+           << mri_->getName(cur->preference) << "\n";
+      return cur->preference;
+    } else
+      DOUT << "\t\tunable to assign the preferred register: "
+           << mri_->getName(cur->preference) << "\n";
+
   // Scan for the first available register.
-  TargetRegisterClass::iterator I = rc->allocation_order_begin(*mf_);
-  TargetRegisterClass::iterator E = rc->allocation_order_end(*mf_);
+  TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
+  TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
   for (; I != E; ++I)
     if (prt_->isRegAvail(*I)) {
       FreeReg = *I;