refactor some code, no functionality change

[oota-llvm.git] / lib / CodeGen / RegAllocLinearScan.cpp

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 8ce7e8a73f561e30ef19d817e1e40dfd8673b987..8ad347bb7dad15fa90e7c4a2141b701e4dfd96dd 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -61,7 +61,6 @@ namespace {
     const TargetMachine* tm_;
     const MRegisterInfo* mri_;
     LiveIntervals* li_;
-    bool *PhysRegsUsed;
 
     /// handled_ - Intervals are added to the handled_ set in the order of their
     /// start value.  This is uses for backtracking.
@@ -194,10 +193,6 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
   if (RelatedRegClasses.empty())
     ComputeRelatedRegClasses();
   
-  PhysRegsUsed = new bool[mri_->getNumRegs()];
-  std::fill(PhysRegsUsed, PhysRegsUsed+mri_->getNumRegs(), false);
-  fn.setUsedPhysRegs(PhysRegsUsed);
-
   if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_));
   vrm_.reset(new VirtRegMap(*mf_));
   if (!spiller_.get()) spiller_.reset(createSpiller());
@@ -231,7 +226,7 @@ void RA::initIntervalSets()
 
   for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
     if (MRegisterInfo::isPhysicalRegister(i->second.reg)) {
-      PhysRegsUsed[i->second.reg] = true;
+      mf_->setPhysRegUsed(i->second.reg);
       fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
     } else
       unhandled_.push(&i->second);
@@ -563,15 +558,17 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
 
   // Find a register to spill.
   float minWeight = HUGE_VALF;
-  unsigned minReg = 0;
-  for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
-       e = RC->allocation_order_end(*mf_); i != e; ++i) {
-    unsigned reg = *i;
-    if (minWeight > SpillWeights[reg]) {
-      minWeight = SpillWeights[reg];
-      minReg = reg;
+  unsigned minReg = cur->preference;  // Try the preferred register first.
+  
+  if (!minReg || SpillWeights[minReg] == HUGE_VALF)
+    for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
+           e = RC->allocation_order_end(*mf_); i != e; ++i) {
+      unsigned reg = *i;
+      if (minWeight > SpillWeights[reg]) {
+        minWeight = SpillWeights[reg];
+        minReg = reg;
+      }
     }
-  }
   
   // If we didn't find a register that is spillable, try aliases?
   if (!minReg) {
@@ -774,14 +771,23 @@ unsigned RA::getFreePhysReg(LiveInterval *cur) {
     }
   }
 
-  const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
-
   unsigned FreeReg = 0;
   unsigned FreeRegInactiveCount = 0;
-  
+
+  // If copy coalescer has assigned a "preferred" register, check if it's
+  // available first.
+  if (cur->preference)
+    if (prt_->isRegAvail(cur->preference)) {
+      DOUT << "\t\tassigned the preferred register: "
+           << mri_->getName(cur->preference) << "\n";
+      return cur->preference;
+    } else
+      DOUT << "\t\tunable to assign the preferred register: "
+           << mri_->getName(cur->preference) << "\n";
+
   // Scan for the first available register.
-  TargetRegisterClass::iterator I = rc->allocation_order_begin(*mf_);
-  TargetRegisterClass::iterator E = rc->allocation_order_end(*mf_);
+  TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
+  TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
   for (; I != E; ++I)
     if (prt_->isRegAvail(*I)) {
       FreeReg = *I;