Changed option name from inline-threshold to basic-inline-threshold because

[oota-llvm.git] / lib / CodeGen / RegAllocLinearScan.cpp

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index ede387e7b79fddbfe18919167ec705b1e81303c1..a9444619fa5d239120a79ad663911d361e09af15 100644 (file)
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -29,6 +29,7 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/ADT/EquivalenceClasses.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/Debug.h"
@@ -49,6 +50,11 @@ NewHeuristic("new-spilling-heuristic",
              cl::desc("Use new spilling heuristic"),
              cl::init(false), cl::Hidden);
 
+static cl::opt<bool>
+PreSplitIntervals("pre-alloc-split",
+                  cl::desc("Pre-register allocation live interval splitting"),
+                  cl::init(false), cl::Hidden);
+
 static RegisterRegAlloc
 linearscanRegAlloc("linearscan", "linear scan register allocator",
                    createLinearScanRegisterAllocator);
@@ -113,6 +119,8 @@ namespace {
       // Make sure PassManager knows which analyses to make available
       // to coalescing and which analyses coalescing invalidates.
       AU.addRequiredTransitive<RegisterCoalescer>();
+      if (PreSplitIntervals)
+        AU.addRequiredID(PreAllocSplittingID);
       AU.addRequired<LiveStacks>();
       AU.addPreserved<LiveStacks>();
       AU.addRequired<MachineLoopInfo>();
@@ -241,12 +249,13 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
   if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
     return Reg;
 
-  VNInfo *vni = cur.getValNumInfo(0);
+  VNInfo *vni = cur.begin()->valno;
   if (!vni->def || vni->def == ~1U || vni->def == ~0U)
     return Reg;
   MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
-  unsigned SrcReg, DstReg;
-  if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
+  unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+  if (!CopyMI ||
+      !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
     return Reg;
   if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
     if (!vrm_->isAssignedReg(SrcReg))
@@ -403,7 +412,7 @@ void RALinScan::linearScan()
     for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
          I != E; ++I) {
       const LiveRange &LR = *I;
-      if (li_->findLiveInMBBs(LR, LiveInMBBs)) {
+      if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
         for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
           if (LiveInMBBs[i] != EntryMBB)
             LiveInMBBs[i]->addLiveIn(Reg);
@@ -543,7 +552,7 @@ static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
   SI.weight += Weight;
 
   VNInfo *VNI;
-  if (SI.getNumValNums())
+  if (SI.hasAtLeastOneValue())
     VNI = SI.getValNumInfo(0);
   else
     VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
@@ -678,17 +687,18 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
   unsigned StartPosition = cur->beginNumber();
   const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
 
-  // If this live interval is defined by a move instruction and its source is
-  // assigned a physical register that is compatible with the target register
-  // class, then we should try to assign it the same register.
+  // If start of this live interval is defined by a move instruction and its
+  // source is assigned a physical register that is compatible with the target
+  // register class, then we should try to assign it the same register.
   // This can happen when the move is from a larger register class to a smaller
   // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
-  if (!cur->preference && cur->containsOneValue()) {
-    VNInfo *vni = cur->getValNumInfo(0);
+  if (!cur->preference && cur->hasAtLeastOneValue()) {
+    VNInfo *vni = cur->begin()->valno;
     if (vni->def && vni->def != ~1U && vni->def != ~0U) {
       MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
-      unsigned SrcReg, DstReg;
-      if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
+      unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+      if (CopyMI &&
+          tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
         unsigned Reg = 0;
         if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
           Reg = SrcReg;