//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements a linear scan register allocator.
//
//===----------------------------------------------------------------------===//
+
#define DEBUG_TYPE "regalloc"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "PhysRegTracker.h"
+#include "VirtRegMap.h"
#include "llvm/Function.h"
-#include "llvm/CodeGen/LiveIntervals.h"
-#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/SSARegMap.h"
-#include "llvm/Target/MRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/RegAllocRegistry.h"
+#include "llvm/CodeGen/RegisterCoalescer.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegInfo.h"
-#include "llvm/Support/CFG.h"
-#include "Support/Debug.h"
-#include "Support/DepthFirstIterator.h"
-#include "Support/Statistic.h"
-#include "Support/STLExtras.h"
-#include <iostream>
-
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/ADT/EquivalenceClasses.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Compiler.h"
+#include <algorithm>
+#include <set>
+#include <queue>
+#include <memory>
+#include <cmath>
using namespace llvm;
-namespace {
- Statistic<> numSpilled ("ra-linearscan", "Number of registers spilled");
-
- class RA : public MachineFunctionPass {
- public:
- typedef std::vector<const LiveIntervals::Interval*> IntervalPtrs;
-
- private:
- MachineFunction* mf_;
- const TargetMachine* tm_;
- const MRegisterInfo* mri_;
- MachineBasicBlock* currentMbb_;
- MachineBasicBlock::iterator currentInstr_;
- typedef LiveIntervals::Intervals Intervals;
- const Intervals* li_;
- IntervalPtrs active_, inactive_;
-
- typedef std::vector<unsigned> Regs;
- Regs tempUseOperands_;
- Regs tempDefOperands_;
-
- Regs reserved_;
-
- typedef LiveIntervals::MachineBasicBlockPtrs MachineBasicBlockPtrs;
- MachineBasicBlockPtrs mbbs_;
-
- typedef std::vector<unsigned> Phys2VirtMap;
- Phys2VirtMap p2vMap_;
-
- typedef std::map<unsigned, unsigned> Virt2PhysMap;
- Virt2PhysMap v2pMap_;
+STATISTIC(NumIters , "Number of iterations performed");
+STATISTIC(NumBacktracks, "Number of times we had to backtrack");
+STATISTIC(NumCoalesce, "Number of copies coalesced");
- typedef std::map<unsigned, int> Virt2StackSlotMap;
- Virt2StackSlotMap v2ssMap_;
+static RegisterRegAlloc
+linearscanRegAlloc("linearscan", " linear scan register allocator",
+ createLinearScanRegisterAllocator);
- int instrAdded_;
-
- public:
- virtual const char* getPassName() const {
- return "Linear Scan Register Allocator";
- }
-
- virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- AU.addRequired<LiveVariables>();
- AU.addRequired<LiveIntervals>();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
-
- private:
- /// runOnMachineFunction - register allocate the whole function
- bool runOnMachineFunction(MachineFunction&);
-
- /// processActiveIntervals - expire old intervals and move
- /// non-overlapping ones to the incative list
- void processActiveIntervals(Intervals::const_iterator cur);
-
- /// processInactiveIntervals - expire old intervals and move
- /// overlapping ones to the active list
- void processInactiveIntervals(Intervals::const_iterator cur);
-
- /// assignStackSlotAtInterval - choose and spill
- /// interval. Currently we spill the interval with the last
- /// end point in the active and inactive lists and the current
- /// interval
- void assignStackSlotAtInterval(Intervals::const_iterator cur);
-
- ///
- /// register handling helpers
- ///
-
- /// reservePhysReg - reserves a physical register and spills
- /// any value assigned to it if any
- void reservePhysReg(unsigned reg);
-
- /// clearReservedPhysReg - marks pysical register as free for
- /// use
- void clearReservedPhysReg(unsigned reg);
-
- /// physRegAvailable - returns true if the specifed physical
- /// register is available
- bool physRegAvailable(unsigned physReg);
-
- /// getFreePhysReg - return a free physical register for this
- /// virtual register if we have one, otherwise return 0
- unsigned getFreePhysReg(unsigned virtReg);
-
-
- /// tempPhysRegAvailable - returns true if the specifed
- /// temporary physical register is available
- bool tempPhysRegAvailable(unsigned physReg);
-
- /// getFreeTempPhysReg - return a free temprorary physical
- /// register for this register class if we have one (should
- /// never return 0)
- unsigned getFreeTempPhysReg(const TargetRegisterClass* rc);
-
- /// getFreeTempPhysReg - return a free temprorary physical
- /// register for this virtual register if we have one (should
- /// never return 0)
- unsigned getFreeTempPhysReg(unsigned virtReg) {
- const TargetRegisterClass* rc =
- mf_->getSSARegMap()->getRegClass(virtReg);
- return getFreeTempPhysReg(rc);
- }
-
- /// assignVirt2PhysReg - assigns the free physical register to
- /// the virtual register passed as arguments
- void assignVirt2PhysReg(unsigned virtReg, unsigned physReg);
-
- /// clearVirtReg - free the physical register associated with this
- /// virtual register and disassociate virtual->physical and
- /// physical->virtual mappings
- void clearVirtReg(unsigned virtReg);
-
- /// assignVirt2StackSlot - assigns this virtual register to a
- /// stack slot
- void assignVirt2StackSlot(unsigned virtReg);
-
- /// getStackSlot - returns the offset of the specified
- /// register on the stack
- int getStackSlot(unsigned virtReg);
-
- /// spillVirtReg - spills the virtual register
- void spillVirtReg(unsigned virtReg);
-
- /// loadPhysReg - loads to the physical register the value of
- /// the virtual register specifed. Virtual register must have
- /// an assigned stack slot
- void loadVirt2PhysReg(unsigned virtReg, unsigned physReg);
-
- void printVirt2PhysMap() const {
- std::cerr << "allocated registers:\n";
- for (Virt2PhysMap::const_iterator
- i = v2pMap_.begin(), e = v2pMap_.end(); i != e; ++i) {
- std::cerr << '[' << i->first << ','
- << mri_->getName(i->second) << "]\n";
- }
- std::cerr << '\n';
- }
- void printIntervals(const char* const str,
- RA::IntervalPtrs::const_iterator i,
- RA::IntervalPtrs::const_iterator e) const {
- if (str) std::cerr << str << " intervals:\n";
- for (; i != e; ++i) {
- std::cerr << "\t\t" << **i << " -> ";
- if ((*i)->reg < MRegisterInfo::FirstVirtualRegister) {
- std::cerr << mri_->getName((*i)->reg);
- }
- else {
- std::cerr << mri_->getName(v2pMap_.find((*i)->reg)->second);
- }
- std::cerr << '\n';
- }
- }
- };
-}
-
-bool RA::runOnMachineFunction(MachineFunction &fn) {
- mf_ = &fn;
- tm_ = &fn.getTarget();
- mri_ = tm_->getRegisterInfo();
- li_ = &getAnalysis<LiveIntervals>().getIntervals();
- active_.clear();
- inactive_.clear();
- mbbs_ = getAnalysis<LiveIntervals>().getOrderedMachineBasicBlockPtrs();
- p2vMap_.resize(MRegisterInfo::FirstVirtualRegister-1);
- p2vMap_.clear();
- v2pMap_.clear();
- v2ssMap_.clear();
-
- DEBUG(
- unsigned i = 0;
- for (MachineBasicBlockPtrs::iterator
- mbbi = mbbs_.begin(), mbbe = mbbs_.end();
- mbbi != mbbe; ++mbbi) {
- MachineBasicBlock* mbb = *mbbi;
- std::cerr << mbb->getBasicBlock()->getName() << '\n';
- for (MachineBasicBlock::iterator
- ii = mbb->begin(), ie = mbb->end();
- ii != ie; ++ii) {
- MachineInstr* instr = *ii;
-
- std::cerr << i++ << "\t";
- instr->print(std::cerr, *tm_);
- }
- }
- );
-
- // FIXME: this will work only for the X86 backend. I need to
- // device an algorthm to select the minimal (considering register
- // aliasing) number of temp registers to reserve so that we have 2
- // registers for each register class available.
-
- // reserve R32: EDI, EBX,
- // R16: DI, BX,
- // R8: BH, BL
- // RFP: FP5, FP6
- reserved_.push_back(19); /* EDI */
- reserved_.push_back(17); /* EBX */
- reserved_.push_back(12); /* DI */
- reserved_.push_back( 7); /* BX */
- reserved_.push_back( 4); /* BH */
- reserved_.push_back( 5); /* BL */
- reserved_.push_back(28); /* FP5 */
- reserved_.push_back(29); /* FP6 */
-
- // liner scan algorithm
- for (Intervals::const_iterator
- i = li_->begin(), e = li_->end(); i != e; ++i) {
- DEBUG(std::cerr << "processing current interval: " << *i << '\n');
-
- DEBUG(printIntervals("\tactive", active_.begin(), active_.end()));
- DEBUG(printIntervals("\tinactive", inactive_.begin(), inactive_.end()));
- processActiveIntervals(i);
- // processInactiveIntervals(i);
-
- // if this register is preallocated, look for an interval that
- // overlaps with it and assign it to a memory location
- if (i->reg < MRegisterInfo::FirstVirtualRegister) {
- reservePhysReg(i->reg);
- active_.push_back(&*i);
- }
- // otherwise we are allocating a virtual register. try to find
- // a free physical register or spill an interval in order to
- // assign it one (we could spill the current though).
- else {
- unsigned physReg = getFreePhysReg(i->reg);
- if (!physReg) {
- assignStackSlotAtInterval(i);
- }
- else {
- assignVirt2PhysReg(i->reg, physReg);
- active_.push_back(&*i);
- }
- }
+namespace {
+ struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
+ static char ID;
+ RALinScan() : MachineFunctionPass((intptr_t)&ID) {}
+
+ typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
+ typedef std::vector<IntervalPtr> IntervalPtrs;
+ private:
+ /// RelatedRegClasses - This structure is built the first time a function is
+ /// compiled, and keeps track of which register classes have registers that
+ /// belong to multiple classes or have aliases that are in other classes.
+ EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
+ std::map<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
+
+ MachineFunction* mf_;
+ const TargetMachine* tm_;
+ const TargetRegisterInfo* tri_;
+ const TargetInstrInfo* tii_;
+ MachineRegisterInfo *reginfo_;
+ BitVector allocatableRegs_;
+ LiveIntervals* li_;
+ const MachineLoopInfo *loopInfo;
+
+ /// handled_ - Intervals are added to the handled_ set in the order of their
+ /// start value. This is uses for backtracking.
+ std::vector<LiveInterval*> handled_;
+
+ /// fixed_ - Intervals that correspond to machine registers.
+ ///
+ IntervalPtrs fixed_;
+
+ /// active_ - Intervals that are currently being processed, and which have a
+ /// live range active for the current point.
+ IntervalPtrs active_;
+
+ /// inactive_ - Intervals that are currently being processed, but which have
+ /// a hold at the current point.
+ IntervalPtrs inactive_;
+
+ typedef std::priority_queue<LiveInterval*,
+ std::vector<LiveInterval*>,
+ greater_ptr<LiveInterval> > IntervalHeap;
+ IntervalHeap unhandled_;
+ std::auto_ptr<PhysRegTracker> prt_;
+ std::auto_ptr<VirtRegMap> vrm_;
+ std::auto_ptr<Spiller> spiller_;
+
+ public:
+ virtual const char* getPassName() const {
+ return "Linear Scan Register Allocator";
}
- // expire any remaining active intervals
- for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
- unsigned reg = (*i)->reg;
- DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
- if (reg < MRegisterInfo::FirstVirtualRegister) {
- clearReservedPhysReg(reg);
- }
- else {
- p2vMap_[v2pMap_[reg]] = 0;
- }
- // remove interval from active
+
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<LiveIntervals>();
+ // Make sure PassManager knows which analyses to make available
+ // to coalescing and which analyses coalescing invalidates.
+ AU.addRequiredTransitive<RegisterCoalescer>();
+ AU.addRequired<MachineLoopInfo>();
+ AU.addPreserved<MachineLoopInfo>();
+ AU.addPreservedID(MachineDominatorsID);
+ MachineFunctionPass::getAnalysisUsage(AU);
}
- DEBUG(std::cerr << "finished register allocation\n");
- DEBUG(printVirt2PhysMap());
-
- DEBUG(std::cerr << "Rewrite machine code:\n");
- for (MachineBasicBlockPtrs::iterator
- mbbi = mbbs_.begin(), mbbe = mbbs_.end(); mbbi != mbbe; ++mbbi) {
- instrAdded_ = 0;
- currentMbb_ = *mbbi;
-
- for (currentInstr_ = currentMbb_->begin();
- currentInstr_ != currentMbb_->end(); ++currentInstr_) {
-
- DEBUG(std::cerr << "\tinstruction: ";
- (*currentInstr_)->print(std::cerr, *tm_););
-
- // use our current mapping and actually replace and
- // virtual register with its allocated physical registers
- DEBUG(std::cerr << "\t\treplacing virtual registers with mapped "
- "physical registers:\n");
- for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
- i != e; ++i) {
- MachineOperand& op = (*currentInstr_)->getOperand(i);
- if (op.isVirtualRegister()) {
- unsigned virtReg = op.getAllocatedRegNum();
- unsigned physReg = v2pMap_[virtReg];
- // if this virtual registers lives on the stack,
- // load it to a temporary physical register
- if (physReg) {
- DEBUG(std::cerr << "\t\t\t%reg" << virtReg
- << " -> " << mri_->getName(physReg) << '\n');
- (*currentInstr_)->SetMachineOperandReg(i, physReg);
- }
- }
- }
-
- DEBUG(std::cerr << "\t\tloading temporarily used operands to "
- "registers:\n");
- for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
- i != e; ++i) {
- MachineOperand& op = (*currentInstr_)->getOperand(i);
- if (op.isVirtualRegister() && op.isUse()) {
- unsigned virtReg = op.getAllocatedRegNum();
- unsigned physReg = v2pMap_[virtReg];
- if (!physReg) {
- physReg = getFreeTempPhysReg(virtReg);
- }
- loadVirt2PhysReg(virtReg, physReg);
- tempUseOperands_.push_back(virtReg);
- (*currentInstr_)->SetMachineOperandReg(i, physReg);
- }
- }
-
- DEBUG(std::cerr << "\t\tclearing temporarily used operands:\n");
- for (unsigned i = 0, e = tempUseOperands_.size(); i != e; ++i) {
- clearVirtReg(tempUseOperands_[i]);
- }
- tempUseOperands_.clear();
-
- DEBUG(std::cerr << "\t\tassigning temporarily defined operands to "
- "registers:\n");
- for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
- i != e; ++i) {
- MachineOperand& op = (*currentInstr_)->getOperand(i);
- if (op.isVirtualRegister() && op.isDef()) {
- unsigned virtReg = op.getAllocatedRegNum();
- unsigned physReg = v2pMap_[virtReg];
- if (!physReg) {
- physReg = getFreeTempPhysReg(virtReg);
- }
- if (op.isUse()) { // def and use
- loadVirt2PhysReg(virtReg, physReg);
- }
- else {
- assignVirt2PhysReg(virtReg, physReg);
- }
- tempDefOperands_.push_back(virtReg);
- (*currentInstr_)->SetMachineOperandReg(i, physReg);
- }
- }
-
-
- // if the instruction is a two address instruction and the
- // source operands are not identical we need to insert
- // extra instructions.
-
- unsigned opcode = (*currentInstr_)->getOpcode();
- if (tm_->getInstrInfo().isTwoAddrInstr(opcode) &&
- (*currentInstr_)->getOperand(0).getAllocatedRegNum() !=
- (*currentInstr_)->getOperand(1).getAllocatedRegNum()) {
- assert((*currentInstr_)->getOperand(1).isRegister() &&
- (*currentInstr_)->getOperand(1).getAllocatedRegNum() &&
- (*currentInstr_)->getOperand(1).isUse() &&
- "Two address instruction invalid");
-
- unsigned regA =
- (*currentInstr_)->getOperand(0).getAllocatedRegNum();
- unsigned regB =
- (*currentInstr_)->getOperand(1).getAllocatedRegNum();
- unsigned regC =
- ((*currentInstr_)->getNumOperands() > 2 &&
- (*currentInstr_)->getOperand(2).isRegister()) ?
- (*currentInstr_)->getOperand(2).getAllocatedRegNum() :
- 0;
-
- const TargetRegisterClass* rc = mri_->getRegClass(regA);
-
- // special case: "a = b op a". If b is a temporary
- // reserved register rewrite as: "b = b op a; a = b"
- // otherwise use a temporary reserved register t and
- // rewrite as: "t = b; t = t op a; a = t"
- if (regC && regA == regC) {
- // b is a temp reserved register
- if (find(reserved_.begin(), reserved_.end(),
- regB) != reserved_.end()) {
- (*currentInstr_)->SetMachineOperandReg(0, regB);
- ++currentInstr_;
- instrAdded_ += mri_->copyRegToReg(*currentMbb_,
- currentInstr_,
- regA,
- regB,
- rc);
- --currentInstr_;
- }
- // b is just a normal register
- else {
- unsigned tempReg = getFreeTempPhysReg(rc);
- assert (tempReg &&
- "no free temp reserved physical register?");
- instrAdded_ += mri_->copyRegToReg(*currentMbb_,
- currentInstr_,
- tempReg,
- regB,
- rc);
- (*currentInstr_)->SetMachineOperandReg(0, tempReg);
- (*currentInstr_)->SetMachineOperandReg(1, tempReg);
- ++currentInstr_;
- instrAdded_ += mri_->copyRegToReg(*currentMbb_,
- currentInstr_,
- regA,
- tempReg,
- rc);
- --currentInstr_;
- }
- }
- // "a = b op c" gets rewritten to "a = b; a = a op c"
- else {
- instrAdded_ += mri_->copyRegToReg(*currentMbb_,
- currentInstr_,
- regA,
- regB,
- rc);
- (*currentInstr_)->SetMachineOperandReg(1, regA);
- }
- }
-
- DEBUG(std::cerr << "\t\tspilling temporarily defined operands "
- "of this instruction:\n");
- ++currentInstr_; // we want to insert after this instruction
- for (unsigned i = 0, e = tempDefOperands_.size(); i != e; ++i) {
- spillVirtReg(tempDefOperands_[i]);
- }
- --currentInstr_; // restore currentInstr_ iterator
- tempDefOperands_.clear();
+ /// runOnMachineFunction - register allocate the whole function
+ bool runOnMachineFunction(MachineFunction&);
+
+ private:
+ /// linearScan - the linear scan algorithm
+ void linearScan();
+
+ /// initIntervalSets - initialize the interval sets.
+ ///
+ void initIntervalSets();
+
+ /// processActiveIntervals - expire old intervals and move non-overlapping
+ /// ones to the inactive list.
+ void processActiveIntervals(unsigned CurPoint);
+
+ /// processInactiveIntervals - expire old intervals and move overlapping
+ /// ones to the active list.
+ void processInactiveIntervals(unsigned CurPoint);
+
+ /// assignRegOrStackSlotAtInterval - assign a register if one
+ /// is available, or spill.
+ void assignRegOrStackSlotAtInterval(LiveInterval* cur);
+
+ /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
+ /// try allocate the definition the same register as the source register
+ /// if the register is not defined during live time of the interval. This
+ /// eliminate a copy. This is used to coalesce copies which were not
+ /// coalesced away before allocation either due to dest and src being in
+ /// different register classes or because the coalescer was overly
+ /// conservative.
+ unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
+
+ ///
+ /// register handling helpers
+ ///
+
+ /// getFreePhysReg - return a free physical register for this virtual
+ /// register interval if we have one, otherwise return 0.
+ unsigned getFreePhysReg(LiveInterval* cur);
+
+ /// assignVirt2StackSlot - assigns this virtual register to a
+ /// stack slot. returns the stack slot
+ int assignVirt2StackSlot(unsigned virtReg);
+
+ void ComputeRelatedRegClasses();
+
+ template <typename ItTy>
+ void printIntervals(const char* const str, ItTy i, ItTy e) const {
+ if (str) DOUT << str << " intervals:\n";
+ for (; i != e; ++i) {
+ DOUT << "\t" << *i->first << " -> ";
+ unsigned reg = i->first->reg;
+ if (TargetRegisterInfo::isVirtualRegister(reg)) {
+ reg = vrm_->getPhys(reg);
}
+ DOUT << tri_->getName(reg) << '\n';
+ }
+ }
+ };
+ char RALinScan::ID = 0;
+}
- for (unsigned i = 0, e = p2vMap_.size(); i != e; ++i) {
- assert(p2vMap_[i] != i &&
- "reserved physical registers at end of basic block?");
- }
+void RALinScan::ComputeRelatedRegClasses() {
+ const TargetRegisterInfo &TRI = *tri_;
+
+ // First pass, add all reg classes to the union, and determine at least one
+ // reg class that each register is in.
+ bool HasAliases = false;
+ for (TargetRegisterInfo::regclass_iterator RCI = TRI.regclass_begin(),
+ E = TRI.regclass_end(); RCI != E; ++RCI) {
+ RelatedRegClasses.insert(*RCI);
+ for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
+ I != E; ++I) {
+ HasAliases = HasAliases || *TRI.getAliasSet(*I) != 0;
+
+ const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
+ if (PRC) {
+ // Already processed this register. Just make sure we know that
+ // multiple register classes share a register.
+ RelatedRegClasses.unionSets(PRC, *RCI);
+ } else {
+ PRC = *RCI;
+ }
}
+ }
+
+ // Second pass, now that we know conservatively what register classes each reg
+ // belongs to, add info about aliases. We don't need to do this for targets
+ // without register aliases.
+ if (HasAliases)
+ for (std::map<unsigned, const TargetRegisterClass*>::iterator
+ I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
+ I != E; ++I)
+ for (const unsigned *AS = TRI.getAliasSet(I->first); *AS; ++AS)
+ RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
+}
- return true;
+/// attemptTrivialCoalescing - If a simple interval is defined by a copy,
+/// try allocate the definition the same register as the source register
+/// if the register is not defined during live time of the interval. This
+/// eliminate a copy. This is used to coalesce copies which were not
+/// coalesced away before allocation either due to dest and src being in
+/// different register classes or because the coalescer was overly
+/// conservative.
+unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
+ if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
+ return Reg;
+
+ VNInfo *vni = cur.getValNumInfo(0);
+ if (!vni->def || vni->def == ~1U || vni->def == ~0U)
+ return Reg;
+ MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
+ unsigned SrcReg, DstReg;
+ if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
+ return Reg;
+ if (TargetRegisterInfo::isVirtualRegister(SrcReg))
+ if (!vrm_->isAssignedReg(SrcReg))
+ return Reg;
+ else
+ SrcReg = vrm_->getPhys(SrcReg);
+ if (Reg == SrcReg)
+ return Reg;
+
+ const TargetRegisterClass *RC = reginfo_->getRegClass(cur.reg);
+ if (!RC->contains(SrcReg))
+ return Reg;
+
+ // Try to coalesce.
+ if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
+ DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg) << '\n';
+ vrm_->clearVirt(cur.reg);
+ vrm_->assignVirt2Phys(cur.reg, SrcReg);
+ ++NumCoalesce;
+ return SrcReg;
+ }
+
+ return Reg;
}
-void RA::processActiveIntervals(Intervals::const_iterator cur)
-{
- DEBUG(std::cerr << "\tprocessing active intervals:\n");
- for (IntervalPtrs::iterator i = active_.begin(); i != active_.end();) {
- unsigned reg = (*i)->reg;
- // remove expired intervals. we expire earlier because this if
- // an interval expires this is going to be the last use. in
- // this case we can reuse the register for a def in the same
- // instruction
- if ((*i)->expiredAt(cur->start() + 1)) {
- DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
- if (reg < MRegisterInfo::FirstVirtualRegister) {
- clearReservedPhysReg(reg);
- }
- else {
- p2vMap_[v2pMap_[reg]] = 0;
- }
- // remove interval from active
- i = active_.erase(i);
- }
- // move not active intervals to inactive list
-// else if (!(*i)->overlaps(curIndex)) {
-// DEBUG(std::cerr << "\t\t\tinterval " << **i << " inactive\n");
-// unmarkReg(virtReg);
-// // add interval to inactive
-// inactive_.push_back(*i);
-// // remove interval from active
-// i = active_.erase(i);
-// }
- else {
- ++i;
- }
- }
+bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
+ mf_ = &fn;
+ tm_ = &fn.getTarget();
+ tri_ = tm_->getRegisterInfo();
+ tii_ = tm_->getInstrInfo();
+ reginfo_ = &mf_->getRegInfo();
+ allocatableRegs_ = tri_->getAllocatableSet(fn);
+ li_ = &getAnalysis<LiveIntervals>();
+ loopInfo = &getAnalysis<MachineLoopInfo>();
+
+ // We don't run the coalescer here because we have no reason to
+ // interact with it. If the coalescer requires interaction, it
+ // won't do anything. If it doesn't require interaction, we assume
+ // it was run as a separate pass.
+
+ // If this is the first function compiled, compute the related reg classes.
+ if (RelatedRegClasses.empty())
+ ComputeRelatedRegClasses();
+
+ if (!prt_.get()) prt_.reset(new PhysRegTracker(*tri_));
+ vrm_.reset(new VirtRegMap(*mf_));
+ if (!spiller_.get()) spiller_.reset(createSpiller());
+
+ initIntervalSets();
+
+ linearScan();
+
+ // Rewrite spill code and update the PhysRegsUsed set.
+ spiller_->runOnMachineFunction(*mf_, *vrm_);
+ vrm_.reset(); // Free the VirtRegMap
+
+ while (!unhandled_.empty()) unhandled_.pop();
+ fixed_.clear();
+ active_.clear();
+ inactive_.clear();
+ handled_.clear();
+
+ return true;
}
-void RA::processInactiveIntervals(Intervals::const_iterator cur)
+/// initIntervalSets - initialize the interval sets.
+///
+void RALinScan::initIntervalSets()
{
-// DEBUG(std::cerr << "\tprocessing inactive intervals:\n");
-// for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end();) {
-// unsigned virtReg = (*i)->reg;
-// // remove expired intervals
-// if ((*i)->expired(curIndex)) {
-// DEBUG(std::cerr << "\t\t\tinterval " << **i << " expired\n");
-// freePhysReg(virtReg);
-// // remove from inactive
-// i = inactive_.erase(i);
-// }
-// // move re-activated intervals in active list
-// else if ((*i)->overlaps(curIndex)) {
-// DEBUG(std::cerr << "\t\t\tinterval " << **i << " active\n");
-// markReg(virtReg);
-// // add to active
-// active_.push_back(*i);
-// // remove from inactive
-// i = inactive_.erase(i);
-// }
-// else {
-// ++i;
-// }
-// }
+ assert(unhandled_.empty() && fixed_.empty() &&
+ active_.empty() && inactive_.empty() &&
+ "interval sets should be empty on initialization");
+
+ for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
+ if (TargetRegisterInfo::isPhysicalRegister(i->second.reg)) {
+ reginfo_->setPhysRegUsed(i->second.reg);
+ fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
+ } else
+ unhandled_.push(&i->second);
+ }
}
-void RA::assignStackSlotAtInterval(Intervals::const_iterator cur)
+void RALinScan::linearScan()
{
- DEBUG(std::cerr << "\t\tassigning stack slot at interval "
- << *cur << ":\n");
- assert(!active_.empty() &&
- "active set cannot be empty when choosing a register to spill");
- const TargetRegisterClass* rcCur =
- mf_->getSSARegMap()->getRegClass(cur->reg);
-
- // find the interval for a virtual register that ends last in
- // active and belongs to the same register class as the current
- // interval
- IntervalPtrs::iterator lastEndActive = active_.begin();
- for (IntervalPtrs::iterator e = active_.end();
- lastEndActive != e; ++lastEndActive) {
- if ((*lastEndActive)->reg >= MRegisterInfo::FirstVirtualRegister) {
- const TargetRegisterClass* rc =
- mri_->getRegClass(v2pMap_[(*lastEndActive)->reg]);
- if (rcCur == rc) {
- break;
- }
- }
- }
- for (IntervalPtrs::iterator i = lastEndActive, e = active_.end();
- i != e; ++i) {
- if ((*i)->reg >= MRegisterInfo::FirstVirtualRegister) {
- const TargetRegisterClass* rc =
- mri_->getRegClass(v2pMap_[(*i)->reg]);
- if (rcCur == rc &&
- (*lastEndActive)->end() < (*i)->end()) {
- lastEndActive = i;
- }
- }
- }
-
- // find the interval for a virtual register that ends last in
- // inactive and belongs to the same register class as the current
- // interval
- IntervalPtrs::iterator lastEndInactive = inactive_.begin();
- for (IntervalPtrs::iterator e = inactive_.end();
- lastEndInactive != e; ++lastEndInactive) {
- if ((*lastEndInactive)->reg >= MRegisterInfo::FirstVirtualRegister) {
- const TargetRegisterClass* rc =
- mri_->getRegClass(v2pMap_[(*lastEndInactive)->reg]);
- if (rcCur == rc) {
- break;
- }
- }
- }
- for (IntervalPtrs::iterator i = lastEndInactive, e = inactive_.end();
- i != e; ++i) {
- if ((*i)->reg >= MRegisterInfo::FirstVirtualRegister) {
- const TargetRegisterClass* rc =
- mri_->getRegClass(v2pMap_[(*i)->reg]);
- if (rcCur == rc &&
- (*lastEndInactive)->end() < (*i)->end()) {
- lastEndInactive = i;
- }
- }
- }
-
- unsigned lastEndActiveInactive = 0;
- if (lastEndActive != active_.end() &&
- lastEndActiveInactive < (*lastEndActive)->end()) {
- lastEndActiveInactive = (*lastEndActive)->end();
- }
- if (lastEndInactive != inactive_.end() &&
- lastEndActiveInactive < (*lastEndInactive)->end()) {
- lastEndActiveInactive = (*lastEndInactive)->end();
+ // linear scan algorithm
+ DOUT << "********** LINEAR SCAN **********\n";
+ DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
+
+ DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
+
+ while (!unhandled_.empty()) {
+ // pick the interval with the earliest start point
+ LiveInterval* cur = unhandled_.top();
+ unhandled_.pop();
+ ++NumIters;
+ DOUT << "\n*** CURRENT ***: " << *cur << '\n';
+
+ processActiveIntervals(cur->beginNumber());
+ processInactiveIntervals(cur->beginNumber());
+
+ assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
+ "Can only allocate virtual registers!");
+
+ // Allocating a virtual register. try to find a free
+ // physical register or spill an interval (possibly this one) in order to
+ // assign it one.
+ assignRegOrStackSlotAtInterval(cur);
+
+ DEBUG(printIntervals("active", active_.begin(), active_.end()));
+ DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
+ }
+
+ // expire any remaining active intervals
+ while (!active_.empty()) {
+ IntervalPtr &IP = active_.back();
+ unsigned reg = IP.first->reg;
+ DOUT << "\tinterval " << *IP.first << " expired\n";
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
+ "Can only allocate virtual registers!");
+ reg = vrm_->getPhys(reg);
+ prt_->delRegUse(reg);
+ active_.pop_back();
+ }
+
+ // expire any remaining inactive intervals
+ DEBUG(for (IntervalPtrs::reverse_iterator
+ i = inactive_.rbegin(); i != inactive_.rend(); ++i)
+ DOUT << "\tinterval " << *i->first << " expired\n");
+ inactive_.clear();
+
+ // Add live-ins to every BB except for entry. Also perform trivial coalescing.
+ MachineFunction::iterator EntryMBB = mf_->begin();
+ SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
+ for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
+ LiveInterval &cur = i->second;
+ unsigned Reg = 0;
+ bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
+ if (isPhys)
+ Reg = i->second.reg;
+ else if (vrm_->isAssignedReg(cur.reg))
+ Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
+ if (!Reg)
+ continue;
+ // Ignore splited live intervals.
+ if (!isPhys && vrm_->getPreSplitReg(cur.reg))
+ continue;
+ for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
+ I != E; ++I) {
+ const LiveRange &LR = *I;
+ if (li_->findLiveInMBBs(LR, LiveInMBBs)) {
+ for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
+ if (LiveInMBBs[i] != EntryMBB)
+ LiveInMBBs[i]->addLiveIn(Reg);
+ LiveInMBBs.clear();
+ }
}
+ }
- if (lastEndActiveInactive > cur->end()) {
- if (lastEndInactive == inactive_.end() ||
- (*lastEndActive)->end() > (*lastEndInactive)->end()) {
- assignVirt2StackSlot((*lastEndActive)->reg);
- active_.erase(lastEndActive);
- }
- else {
- assignVirt2StackSlot((*lastEndInactive)->reg);
- inactive_.erase(lastEndInactive);
- }
- unsigned physReg = getFreePhysReg(cur->reg);
- assert(physReg && "no free physical register after spill?");
- assignVirt2PhysReg(cur->reg, physReg);
- active_.push_back(&*cur);
- }
- else {
- assignVirt2StackSlot(cur->reg);
- }
+ DOUT << *vrm_;
}
-void RA::reservePhysReg(unsigned physReg)
+/// processActiveIntervals - expire old intervals and move non-overlapping ones
+/// to the inactive list.
+void RALinScan::processActiveIntervals(unsigned CurPoint)
{
- DEBUG(std::cerr << "\t\t\treserving physical register: "
- << mri_->getName(physReg) << '\n');
- // if this register holds a value spill it
- unsigned virtReg = p2vMap_[physReg];
- if (virtReg != 0) {
- assert(virtReg != physReg && "reserving an already reserved phus reg?");
- // remove interval from active
- for (IntervalPtrs::iterator i = active_.begin(), e = active_.end();
- i != e; ++i) {
- if ((*i)->reg == virtReg) {
- active_.erase(i);
- break;
- }
- }
- assignVirt2StackSlot(virtReg);
+ DOUT << "\tprocessing active intervals:\n";
+
+ for (unsigned i = 0, e = active_.size(); i != e; ++i) {
+ LiveInterval *Interval = active_[i].first;
+ LiveInterval::iterator IntervalPos = active_[i].second;
+ unsigned reg = Interval->reg;
+
+ IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
+
+ if (IntervalPos == Interval->end()) { // Remove expired intervals.
+ DOUT << "\t\tinterval " << *Interval << " expired\n";
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
+ "Can only allocate virtual registers!");
+ reg = vrm_->getPhys(reg);
+ prt_->delRegUse(reg);
+
+ // Pop off the end of the list.
+ active_[i] = active_.back();
+ active_.pop_back();
+ --i; --e;
+
+ } else if (IntervalPos->start > CurPoint) {
+ // Move inactive intervals to inactive list.
+ DOUT << "\t\tinterval " << *Interval << " inactive\n";
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
+ "Can only allocate virtual registers!");
+ reg = vrm_->getPhys(reg);
+ prt_->delRegUse(reg);
+ // add to inactive.
+ inactive_.push_back(std::make_pair(Interval, IntervalPos));
+
+ // Pop off the end of the list.
+ active_[i] = active_.back();
+ active_.pop_back();
+ --i; --e;
+ } else {
+ // Otherwise, just update the iterator position.
+ active_[i].second = IntervalPos;
}
- p2vMap_[physReg] = physReg; // this denotes a reserved physical register
-
- // if it also aliases any other registers with values spill them too
- for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
- unsigned virtReg = p2vMap_[*as];
- if (virtReg != 0 && virtReg != *as) {
- // remove interval from active
- for (IntervalPtrs::iterator i = active_.begin(), e = active_.end();
- i != e; ++i) {
- if ((*i)->reg == virtReg) {
- active_.erase(i);
- break;
- }
- }
- assignVirt2StackSlot(virtReg);
- }
- }
-}
-
-void RA::clearReservedPhysReg(unsigned physReg)
-{
- DEBUG(std::cerr << "\t\t\tclearing reserved physical register: "
- << mri_->getName(physReg) << '\n');
- assert(p2vMap_[physReg] == physReg &&
- "attempt to clear a non reserved physical register");
- p2vMap_[physReg] = 0;
+ }
}
-bool RA::physRegAvailable(unsigned physReg)
+/// processInactiveIntervals - expire old intervals and move overlapping
+/// ones to the active list.
+void RALinScan::processInactiveIntervals(unsigned CurPoint)
{
- if (p2vMap_[physReg]) {
- return false;
- }
-
- // if it aliases other registers it is still not free
- for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
- if (p2vMap_[*as]) {
- return false;
- }
- }
-
- // if it is one of the reserved registers it is still not free
- if (find(reserved_.begin(), reserved_.end(), physReg) != reserved_.end()) {
- return false;
+ DOUT << "\tprocessing inactive intervals:\n";
+
+ for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
+ LiveInterval *Interval = inactive_[i].first;
+ LiveInterval::iterator IntervalPos = inactive_[i].second;
+ unsigned reg = Interval->reg;
+
+ IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
+
+ if (IntervalPos == Interval->end()) { // remove expired intervals.
+ DOUT << "\t\tinterval " << *Interval << " expired\n";
+
+ // Pop off the end of the list.
+ inactive_[i] = inactive_.back();
+ inactive_.pop_back();
+ --i; --e;
+ } else if (IntervalPos->start <= CurPoint) {
+ // move re-activated intervals in active list
+ DOUT << "\t\tinterval " << *Interval << " active\n";
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
+ "Can only allocate virtual registers!");
+ reg = vrm_->getPhys(reg);
+ prt_->addRegUse(reg);
+ // add to active
+ active_.push_back(std::make_pair(Interval, IntervalPos));
+
+ // Pop off the end of the list.
+ inactive_[i] = inactive_.back();
+ inactive_.pop_back();
+ --i; --e;
+ } else {
+ // Otherwise, just update the iterator position.
+ inactive_[i].second = IntervalPos;
}
+ }
+}
- return true;
+/// updateSpillWeights - updates the spill weights of the specifed physical
+/// register and its weight.
+static void updateSpillWeights(std::vector<float> &Weights,
+ unsigned reg, float weight,
+ const TargetRegisterInfo *TRI) {
+ Weights[reg] += weight;
+ for (const unsigned* as = TRI->getAliasSet(reg); *as; ++as)
+ Weights[*as] += weight;
}
-unsigned RA::getFreePhysReg(unsigned virtReg)
-{
- DEBUG(std::cerr << "\t\tgetting free physical register: ");
- const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
- TargetRegisterClass::iterator reg = rc->allocation_order_begin(*mf_);
- TargetRegisterClass::iterator regEnd = rc->allocation_order_end(*mf_);
-
- for (; reg != regEnd; ++reg) {
- if (physRegAvailable(*reg)) {
- assert(*reg != 0 && "Cannot use register!");
- DEBUG(std::cerr << mri_->getName(*reg) << '\n');
- return *reg; // Found an unused register!
- }
- }
+static
+RALinScan::IntervalPtrs::iterator
+FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
+ for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
+ I != E; ++I)
+ if (I->first == LI) return I;
+ return IP.end();
+}
- DEBUG(std::cerr << "no free register\n");
- return 0;
+static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
+ for (unsigned i = 0, e = V.size(); i != e; ++i) {
+ RALinScan::IntervalPtr &IP = V[i];
+ LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
+ IP.second, Point);
+ if (I != IP.first->begin()) --I;
+ IP.second = I;
+ }
}
-bool RA::tempPhysRegAvailable(unsigned physReg)
+/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
+/// spill.
+void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
{
- assert(find(reserved_.begin(), reserved_.end(), physReg) != reserved_.end()
- && "cannot call this method with a non reserved temp register");
-
- if (p2vMap_[physReg]) {
- return false;
+ DOUT << "\tallocating current interval: ";
+
+ PhysRegTracker backupPrt = *prt_;
+
+ std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
+ unsigned StartPosition = cur->beginNumber();
+ const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
+ const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
+
+ // If this live interval is defined by a move instruction and its source is
+ // assigned a physical register that is compatible with the target register
+ // class, then we should try to assign it the same register.
+ // This can happen when the move is from a larger register class to a smaller
+ // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
+ if (!cur->preference && cur->containsOneValue()) {
+ VNInfo *vni = cur->getValNumInfo(0);
+ if (vni->def && vni->def != ~1U && vni->def != ~0U) {
+ MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
+ unsigned SrcReg, DstReg;
+ if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
+ unsigned Reg = 0;
+ if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
+ Reg = SrcReg;
+ else if (vrm_->isAssignedReg(SrcReg))
+ Reg = vrm_->getPhys(SrcReg);
+ if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
+ cur->preference = Reg;
+ }
}
-
- // if it aliases other registers it is still not free
- for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
- if (p2vMap_[*as]) {
- return false;
+ }
+
+ // for every interval in inactive we overlap with, mark the
+ // register as not free and update spill weights.
+ for (IntervalPtrs::const_iterator i = inactive_.begin(),
+ e = inactive_.end(); i != e; ++i) {
+ unsigned Reg = i->first->reg;
+ assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
+ "Can only allocate virtual registers!");
+ const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg);
+ // If this is not in a related reg class to the register we're allocating,
+ // don't check it.
+ if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
+ cur->overlapsFrom(*i->first, i->second-1)) {
+ Reg = vrm_->getPhys(Reg);
+ prt_->addRegUse(Reg);
+ SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
+ }
+ }
+
+ // Speculatively check to see if we can get a register right now. If not,
+ // we know we won't be able to by adding more constraints. If so, we can
+ // check to see if it is valid. Doing an exhaustive search of the fixed_ list
+ // is very bad (it contains all callee clobbered registers for any functions
+ // with a call), so we want to avoid doing that if possible.
+ unsigned physReg = getFreePhysReg(cur);
+ if (physReg) {
+ // We got a register. However, if it's in the fixed_ list, we might
+ // conflict with it. Check to see if we conflict with it or any of its
+ // aliases.
+ SmallSet<unsigned, 8> RegAliases;
+ for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
+ RegAliases.insert(*AS);
+
+ bool ConflictsWithFixed = false;
+ for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
+ IntervalPtr &IP = fixed_[i];
+ if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
+ // Okay, this reg is on the fixed list. Check to see if we actually
+ // conflict.
+ LiveInterval *I = IP.first;
+ if (I->endNumber() > StartPosition) {
+ LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
+ IP.second = II;
+ if (II != I->begin() && II->start > StartPosition)
+ --II;
+ if (cur->overlapsFrom(*I, II)) {
+ ConflictsWithFixed = true;
+ break;
+ }
}
+ }
}
+
+ // Okay, the register picked by our speculative getFreePhysReg call turned
+ // out to be in use. Actually add all of the conflicting fixed registers to
+ // prt so we can do an accurate query.
+ if (ConflictsWithFixed) {
+ // For every interval in fixed we overlap with, mark the register as not
+ // free and update spill weights.
+ for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
+ IntervalPtr &IP = fixed_[i];
+ LiveInterval *I = IP.first;
+
+ const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
+ if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
+ I->endNumber() > StartPosition) {
+ LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
+ IP.second = II;
+ if (II != I->begin() && II->start > StartPosition)
+ --II;
+ if (cur->overlapsFrom(*I, II)) {
+ unsigned reg = I->reg;
+ prt_->addRegUse(reg);
+ SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
+ }
+ }
+ }
- return true;
-}
-
-unsigned RA::getFreeTempPhysReg(const TargetRegisterClass* rc)
-{
- DEBUG(std::cerr << "\t\tgetting free temporary physical register: ");
-
- for (Regs::const_iterator
- reg = reserved_.begin(), regEnd = reserved_.end();
- reg != regEnd; ++reg) {
- if (rc == mri_->getRegClass(*reg) && tempPhysRegAvailable(*reg)) {
- assert(*reg != 0 && "Cannot use register!");
- DEBUG(std::cerr << mri_->getName(*reg) << '\n');
- return *reg; // Found an unused register!
+ // Using the newly updated prt_ object, which includes conflicts in the
+ // future, see if there are any registers available.
+ physReg = getFreePhysReg(cur);
+ }
+ }
+
+ // Restore the physical register tracker, removing information about the
+ // future.
+ *prt_ = backupPrt;
+
+ // if we find a free register, we are done: assign this virtual to
+ // the free physical register and add this interval to the active
+ // list.
+ if (physReg) {
+ DOUT << tri_->getName(physReg) << '\n';
+ vrm_->assignVirt2Phys(cur->reg, physReg);
+ prt_->addRegUse(physReg);
+ active_.push_back(std::make_pair(cur, cur->begin()));
+ handled_.push_back(cur);
+ return;
+ }
+ DOUT << "no free registers\n";
+
+ // Compile the spill weights into an array that is better for scanning.
+ std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0);
+ for (std::vector<std::pair<unsigned, float> >::iterator
+ I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
+ updateSpillWeights(SpillWeights, I->first, I->second, tri_);
+
+ // for each interval in active, update spill weights.
+ for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
+ i != e; ++i) {
+ unsigned reg = i->first->reg;
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
+ "Can only allocate virtual registers!");
+ reg = vrm_->getPhys(reg);
+ updateSpillWeights(SpillWeights, reg, i->first->weight, tri_);
+ }
+
+ DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
+
+ // Find a register to spill.
+ float minWeight = HUGE_VALF;
+ unsigned minReg = cur->preference; // Try the preferred register first.
+
+ if (!minReg || SpillWeights[minReg] == HUGE_VALF)
+ for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
+ e = RC->allocation_order_end(*mf_); i != e; ++i) {
+ unsigned reg = *i;
+ if (minWeight > SpillWeights[reg]) {
+ minWeight = SpillWeights[reg];
+ minReg = reg;
+ }
+ }
+
+ // If we didn't find a register that is spillable, try aliases?
+ if (!minReg) {
+ for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
+ e = RC->allocation_order_end(*mf_); i != e; ++i) {
+ unsigned reg = *i;
+ // No need to worry about if the alias register size < regsize of RC.
+ // We are going to spill all registers that alias it anyway.
+ for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
+ if (minWeight > SpillWeights[*as]) {
+ minWeight = SpillWeights[*as];
+ minReg = *as;
}
+ }
}
- assert(0 && "no free temporary physical register?");
- return 0;
-}
-
-void RA::assignVirt2PhysReg(unsigned virtReg, unsigned physReg)
-{
- assert((physRegAvailable(physReg) ||
- find(reserved_.begin(),
- reserved_.end(),
- physReg) != reserved_.end()) &&
- "attempt to allocate to a not available physical register");
- v2pMap_[virtReg] = physReg;
- p2vMap_[physReg] = virtReg;
-}
-
-void RA::clearVirtReg(unsigned virtReg)
-{
- Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
- assert(it != v2pMap_.end() &&
- "attempting to clear a not allocated virtual register");
- unsigned physReg = it->second;
- p2vMap_[physReg] = 0;
- v2pMap_[virtReg] = 0; // this marks that this virtual register
- // lives on the stack
- DEBUG(std::cerr << "\t\t\tcleared register " << mri_->getName(physReg)
- << "\n");
-}
-void RA::assignVirt2StackSlot(unsigned virtReg)
-{
- const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
- int frameIndex = mf_->getFrameInfo()->CreateStackObject(rc);
-
- bool inserted = v2ssMap_.insert(std::make_pair(virtReg, frameIndex)).second;
- assert(inserted &&
- "attempt to assign stack slot to already assigned register?");
- // if the virtual register was previously assigned clear the mapping
- // and free the virtual register
- if (v2pMap_.find(virtReg) != v2pMap_.end()) {
- clearVirtReg(virtReg);
+ // All registers must have inf weight. Just grab one!
+ if (!minReg)
+ minReg = *RC->allocation_order_begin(*mf_);
+ }
+
+ DOUT << "\t\tregister with min weight: "
+ << tri_->getName(minReg) << " (" << minWeight << ")\n";
+
+ // if the current has the minimum weight, we need to spill it and
+ // add any added intervals back to unhandled, and restart
+ // linearscan.
+ if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
+ DOUT << "\t\t\tspilling(c): " << *cur << '\n';
+ std::vector<LiveInterval*> added =
+ li_->addIntervalsForSpills(*cur, loopInfo, *vrm_);
+ if (added.empty())
+ return; // Early exit if all spills were folded.
+
+ // Merge added with unhandled. Note that we know that
+ // addIntervalsForSpills returns intervals sorted by their starting
+ // point.
+ for (unsigned i = 0, e = added.size(); i != e; ++i)
+ unhandled_.push(added[i]);
+ return;
+ }
+
+ ++NumBacktracks;
+
+ // push the current interval back to unhandled since we are going
+ // to re-run at least this iteration. Since we didn't modify it it
+ // should go back right in the front of the list
+ unhandled_.push(cur);
+
+ // otherwise we spill all intervals aliasing the register with
+ // minimum weight, rollback to the interval with the earliest
+ // start point and let the linear scan algorithm run again
+ std::vector<LiveInterval*> added;
+ assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
+ "did not choose a register to spill?");
+ BitVector toSpill(tri_->getNumRegs());
+
+ // We are going to spill minReg and all its aliases.
+ toSpill[minReg] = true;
+ for (const unsigned* as = tri_->getAliasSet(minReg); *as; ++as)
+ toSpill[*as] = true;
+
+ // the earliest start of a spilled interval indicates up to where
+ // in handled we need to roll back
+ unsigned earliestStart = cur->beginNumber();
+
+ // set of spilled vregs (used later to rollback properly)
+ SmallSet<unsigned, 32> spilled;
+
+ // spill live intervals of virtual regs mapped to the physical register we
+ // want to clear (and its aliases). We only spill those that overlap with the
+ // current interval as the rest do not affect its allocation. we also keep
+ // track of the earliest start of all spilled live intervals since this will
+ // mark our rollback point.
+ for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
+ unsigned reg = i->first->reg;
+ if (//TargetRegisterInfo::isVirtualRegister(reg) &&
+ toSpill[vrm_->getPhys(reg)] &&
+ cur->overlapsFrom(*i->first, i->second)) {
+ DOUT << "\t\t\tspilling(a): " << *i->first << '\n';
+ earliestStart = std::min(earliestStart, i->first->beginNumber());
+ std::vector<LiveInterval*> newIs =
+ li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_);
+ std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
+ spilled.insert(reg);
}
- else {
- v2pMap_[virtReg] = 0; // this marks that this virtual register
- // lives on the stack
+ }
+ for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
+ unsigned reg = i->first->reg;
+ if (//TargetRegisterInfo::isVirtualRegister(reg) &&
+ toSpill[vrm_->getPhys(reg)] &&
+ cur->overlapsFrom(*i->first, i->second-1)) {
+ DOUT << "\t\t\tspilling(i): " << *i->first << '\n';
+ earliestStart = std::min(earliestStart, i->first->beginNumber());
+ std::vector<LiveInterval*> newIs =
+ li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_);
+ std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
+ spilled.insert(reg);
+ }
+ }
+
+ DOUT << "\t\trolling back to: " << earliestStart << '\n';
+
+ // Scan handled in reverse order up to the earliest start of a
+ // spilled live interval and undo each one, restoring the state of
+ // unhandled.
+ while (!handled_.empty()) {
+ LiveInterval* i = handled_.back();
+ // If this interval starts before t we are done.
+ if (i->beginNumber() < earliestStart)
+ break;
+ DOUT << "\t\t\tundo changes for: " << *i << '\n';
+ handled_.pop_back();
+
+ // When undoing a live interval allocation we must know if it is active or
+ // inactive to properly update the PhysRegTracker and the VirtRegMap.
+ IntervalPtrs::iterator it;
+ if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
+ active_.erase(it);
+ assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
+ if (!spilled.count(i->reg))
+ unhandled_.push(i);
+ prt_->delRegUse(vrm_->getPhys(i->reg));
+ vrm_->clearVirt(i->reg);
+ } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
+ inactive_.erase(it);
+ assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
+ if (!spilled.count(i->reg))
+ unhandled_.push(i);
+ vrm_->clearVirt(i->reg);
+ } else {
+ assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
+ "Can only allocate virtual registers!");
+ vrm_->clearVirt(i->reg);
+ unhandled_.push(i);
}
-}
-int RA::getStackSlot(unsigned virtReg)
-{
- // use lower_bound so that we can do a possibly O(1) insert later
- // if necessary
- Virt2StackSlotMap::iterator it = v2ssMap_.find(virtReg);
- assert(it != v2ssMap_.end() &&
- "attempt to get stack slot on register that does not live on the stack");
- return it->second;
-}
+ // It interval has a preference, it must be defined by a copy. Clear the
+ // preference now since the source interval allocation may have been undone
+ // as well.
+ i->preference = 0;
+ }
+
+ // Rewind the iterators in the active, inactive, and fixed lists back to the
+ // point we reverted to.
+ RevertVectorIteratorsTo(active_, earliestStart);
+ RevertVectorIteratorsTo(inactive_, earliestStart);
+ RevertVectorIteratorsTo(fixed_, earliestStart);
+
+ // scan the rest and undo each interval that expired after t and
+ // insert it in active (the next iteration of the algorithm will
+ // put it in inactive if required)
+ for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
+ LiveInterval *HI = handled_[i];
+ if (!HI->expiredAt(earliestStart) &&
+ HI->expiredAt(cur->beginNumber())) {
+ DOUT << "\t\t\tundo changes for: " << *HI << '\n';
+ active_.push_back(std::make_pair(HI, HI->begin()));
+ assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
+ prt_->addRegUse(vrm_->getPhys(HI->reg));
+ }
+ }
-void RA::spillVirtReg(unsigned virtReg)
-{
- DEBUG(std::cerr << "\t\t\tspilling register: " << virtReg);
- const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
- int frameIndex = getStackSlot(virtReg);
- DEBUG(std::cerr << " to stack slot #" << frameIndex << '\n');
- ++numSpilled;
- instrAdded_ += mri_->storeRegToStackSlot(*currentMbb_, currentInstr_,
- v2pMap_[virtReg], frameIndex, rc);
- clearVirtReg(virtReg);
+ // merge added with unhandled
+ for (unsigned i = 0, e = added.size(); i != e; ++i)
+ unhandled_.push(added[i]);
}
-void RA::loadVirt2PhysReg(unsigned virtReg, unsigned physReg)
-{
- DEBUG(std::cerr << "\t\t\tloading register: " << virtReg);
- const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
- int frameIndex = getStackSlot(virtReg);
- DEBUG(std::cerr << " from stack slot #" << frameIndex << '\n');
- instrAdded_ += mri_->loadRegFromStackSlot(*currentMbb_, currentInstr_,
- physReg, frameIndex, rc);
- assignVirt2PhysReg(virtReg, physReg);
+/// getFreePhysReg - return a free physical register for this virtual register
+/// interval if we have one, otherwise return 0.
+unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
+ std::vector<unsigned> inactiveCounts(tri_->getNumRegs(), 0);
+ unsigned MaxInactiveCount = 0;
+
+ const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
+ const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
+
+ for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
+ i != e; ++i) {
+ unsigned reg = i->first->reg;
+ assert(TargetRegisterInfo::isVirtualRegister(reg) &&
+ "Can only allocate virtual registers!");
+
+ // If this is not in a related reg class to the register we're allocating,
+ // don't check it.
+ const TargetRegisterClass *RegRC = reginfo_->getRegClass(reg);
+ if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
+ reg = vrm_->getPhys(reg);
+ ++inactiveCounts[reg];
+ MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
+ }
+ }
+
+ unsigned FreeReg = 0;
+ unsigned FreeRegInactiveCount = 0;
+
+ // If copy coalescer has assigned a "preferred" register, check if it's
+ // available first.
+ if (cur->preference)
+ if (prt_->isRegAvail(cur->preference)) {
+ DOUT << "\t\tassigned the preferred register: "
+ << tri_->getName(cur->preference) << "\n";
+ return cur->preference;
+ } else
+ DOUT << "\t\tunable to assign the preferred register: "
+ << tri_->getName(cur->preference) << "\n";
+
+ // Scan for the first available register.
+ TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
+ TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
+ for (; I != E; ++I)
+ if (prt_->isRegAvail(*I)) {
+ FreeReg = *I;
+ FreeRegInactiveCount = inactiveCounts[FreeReg];
+ break;
+ }
+
+ // If there are no free regs, or if this reg has the max inactive count,
+ // return this register.
+ if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) return FreeReg;
+
+ // Continue scanning the registers, looking for the one with the highest
+ // inactive count. Alkis found that this reduced register pressure very
+ // slightly on X86 (in rev 1.94 of this file), though this should probably be
+ // reevaluated now.
+ for (; I != E; ++I) {
+ unsigned Reg = *I;
+ if (prt_->isRegAvail(Reg) && FreeRegInactiveCount < inactiveCounts[Reg]) {
+ FreeReg = Reg;
+ FreeRegInactiveCount = inactiveCounts[Reg];
+ if (FreeRegInactiveCount == MaxInactiveCount)
+ break; // We found the one with the max inactive count.
+ }
+ }
+
+ return FreeReg;
}
FunctionPass* llvm::createLinearScanRegisterAllocator() {
- return new RA();
+ return new RALinScan();
}