#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
+#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Support/Visibility.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/Statistic.h"
#include <algorithm>
using namespace llvm;
namespace {
- Statistic<> NumStores("ra-local", "Number of stores added");
- Statistic<> NumLoads ("ra-local", "Number of loads added");
- Statistic<> NumFolded("ra-local", "Number of loads/stores folded into "
- "instructions");
+ static Statistic<> NumStores("ra-local", "Number of stores added");
+ static Statistic<> NumLoads ("ra-local", "Number of loads added");
+ static Statistic<> NumFolded("ra-local", "Number of loads/stores folded "
+ "into instructions");
+
+ static RegisterRegAlloc
+ localRegAlloc("local", " local register allocator",
+ createLocalRegisterAllocator);
+
+
class VISIBILITY_HIDDEN RA : public MachineFunctionPass {
const TargetMachine *TM;
MachineFunction *MF;
// Virt2PhysRegMap). The value mapped to is the virtual register
// corresponding to the physical register (the inverse of the
// Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
- // because it is used by a future instruction. If the entry for a physical
- // register is -1, then the physical register is "not in the map".
+ // because it is used by a future instruction, and to -2 if it is not
+ // allocatable. If the entry for a physical register is -1, then the
+ // physical register is "not in the map".
//
std::vector<int> PhysRegsUsed;
}
void MarkPhysRegRecentlyUsed(unsigned Reg) {
- if(PhysRegsUseOrder.empty() ||
- PhysRegsUseOrder.back() == Reg) return; // Already most recently used
+ if (PhysRegsUseOrder.empty() ||
+ PhysRegsUseOrder.back() == Reg) return; // Already most recently used
for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
void RA::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
unsigned PhysReg, bool OnlyVirtRegs) {
if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
+ assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
} else {
// If the selected register aliases any other registers, we must make
- // sure that one of the aliases isn't alive...
+ // sure that one of the aliases isn't alive.
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
*AliasSet; ++AliasSet)
- if (PhysRegsUsed[*AliasSet] != -1) // Spill aliased register...
+ if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
+ PhysRegsUsed[*AliasSet] != -2) // If allocatable.
if (PhysRegsUsed[*AliasSet] || !OnlyVirtRegs)
spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
}
// physical register!
assert(PhysRegsUsed[R] != -1 &&
"PhysReg in PhysRegsUseOrder, but is not allocated?");
- if (PhysRegsUsed[R]) {
+ if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
// If the current register is compatible, use it.
if (RC->contains(R)) {
PhysReg = R;
} else {
// If one of the registers aliased to the current register is
// compatible, use it.
- for (const unsigned *AliasSet = RegInfo->getAliasSet(R);
- *AliasSet; ++AliasSet) {
- if (RC->contains(*AliasSet)) {
- PhysReg = *AliasSet; // Take an aliased register
+ for (const unsigned *AliasIt = RegInfo->getAliasSet(R);
+ *AliasIt; ++AliasIt) {
+ if (RC->contains(*AliasIt) &&
+ // If this is pinned down for some reason, don't use it. For
+ // example, if CL is pinned, and we run across CH, don't use
+ // CH as justification for using scavenging ECX (which will
+ // fail).
+ PhysRegsUsed[*AliasIt] != 0 &&
+
+ // Make sure the register is allocatable. Don't allocate SIL on
+ // x86-32.
+ PhysRegsUsed[*AliasIt] != -2) {
+ PhysReg = *AliasIt; // Take an aliased register
break;
}
}
PhysRegsUseOrder.push_back(Reg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
*AliasSet; ++AliasSet) {
- PhysRegsUseOrder.push_back(*AliasSet);
- PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
- PhysRegsEverUsed[*AliasSet] = true;
+ if (PhysRegsUsed[*AliasSet] != -2) {
+ PhysRegsUseOrder.push_back(*AliasSet);
+ PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
+ PhysRegsEverUsed[*AliasSet] = true;
+ }
}
}
}
DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI;
std::cerr << " Regs have values: ";
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
- if (PhysRegsUsed[i] != -1)
+ if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
std::cerr << "[" << RegInfo->getName(i)
<< ",%reg" << PhysRegsUsed[i] << "] ";
std::cerr << "\n");
// Loop over the implicit uses, making sure that they are at the head of the
// use order list, so they don't get reallocated.
- for (const unsigned *ImplicitUses = TID.ImplicitUses;
- *ImplicitUses; ++ImplicitUses)
- MarkPhysRegRecentlyUsed(*ImplicitUses);
+ if (TID.ImplicitUses) {
+ for (const unsigned *ImplicitUses = TID.ImplicitUses;
+ *ImplicitUses; ++ImplicitUses)
+ MarkPhysRegRecentlyUsed(*ImplicitUses);
+ }
// Get the used operands into registers. This has the potential to spill
// incoming values if we are out of registers. Note that we completely
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// here we are looking for only used operands (never def&use)
- if (!MO.isDef() && MO.isRegister() && MO.getReg() &&
+ if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
PhysReg = PhysRegSlot;
PhysRegSlot = 0;
+ } else if (PhysRegsUsed[PhysReg] == -2) {
+ // Unallocatable register dead, ignore.
+ continue;
}
if (PhysReg) {
// are defined, and marking explicit destinations in the PhysRegsUsed map.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isDef() && MO.isRegister() && MO.getReg() &&
+ if (MO.isRegister() && MO.isDef() && MO.getReg() &&
MRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
+ if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
+
PhysRegsEverUsed[Reg] = true;
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
*AliasSet; ++AliasSet) {
- PhysRegsUseOrder.push_back(*AliasSet);
- PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
- PhysRegsEverUsed[*AliasSet] = true;
+ if (PhysRegsUsed[*AliasSet] != -2) {
+ PhysRegsUseOrder.push_back(*AliasSet);
+ PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
+ PhysRegsEverUsed[*AliasSet] = true;
+ }
}
}
}
// Loop over the implicit defs, spilling them as well.
- for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
- *ImplicitDefs; ++ImplicitDefs) {
- unsigned Reg = *ImplicitDefs;
- spillPhysReg(MBB, MI, Reg, true);
- PhysRegsUseOrder.push_back(Reg);
- PhysRegsUsed[Reg] = 0; // It is free and reserved now
- PhysRegsEverUsed[Reg] = true;
+ if (TID.ImplicitDefs) {
+ for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
+ *ImplicitDefs; ++ImplicitDefs) {
+ unsigned Reg = *ImplicitDefs;
+ bool IsNonAllocatable = PhysRegsUsed[Reg] == -2;
+ if (!IsNonAllocatable) {
+ spillPhysReg(MBB, MI, Reg, true);
+ PhysRegsUseOrder.push_back(Reg);
+ PhysRegsUsed[Reg] = 0; // It is free and reserved now
+ }
+ PhysRegsEverUsed[Reg] = true;
- for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
- *AliasSet; ++AliasSet) {
- PhysRegsUseOrder.push_back(*AliasSet);
- PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
- PhysRegsEverUsed[*AliasSet] = true;
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+ *AliasSet; ++AliasSet) {
+ if (PhysRegsUsed[*AliasSet] != -2) {
+ if (!IsNonAllocatable) {
+ PhysRegsUseOrder.push_back(*AliasSet);
+ PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
+ }
+ PhysRegsEverUsed[*AliasSet] = true;
+ }
+ }
}
}
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isDef() && MO.isRegister() && MO.getReg() &&
+ if (MO.isRegister() && MO.isDef() && MO.getReg() &&
MRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
PhysReg = PhysRegSlot;
assert(PhysReg != 0);
PhysRegSlot = 0;
+ } else if (PhysRegsUsed[PhysReg] == -2) {
+ // Unallocatable register dead, ignore.
+ continue;
}
if (PhysReg) {
// Finally, if this is a noop copy instruction, zap it.
unsigned SrcReg, DstReg;
- if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
+ if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) {
+ LV->removeVirtualRegistersKilled(MI);
+ LV->removeVirtualRegistersDead(MI);
MBB.erase(MI);
+ }
}
MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
// Spill all physical registers holding virtual registers now.
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
- if (PhysRegsUsed[i] != -1)
+ if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
if (unsigned VirtReg = PhysRegsUsed[i])
spillVirtReg(MBB, MI, VirtReg, i);
else
Fn.setUsedPhysRegs(PhysRegsEverUsed);
PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
+
+ // At various places we want to efficiently check to see whether a register
+ // is allocatable. To handle this, we mark all unallocatable registers as
+ // being pinned down, permanently.
+ {
+ std::vector<bool> Allocable = RegInfo->getAllocatableSet(Fn);
+ for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
+ if (!Allocable[i])
+ PhysRegsUsed[i] = -2; // Mark the reg unallocable.
+ }
// initialize the virtual->physical register map to have a 'null'
// mapping for all virtual registers
projects / oota-llvm.git / blobdiff