// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
+//
// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
// register allocator for LLVM. This allocator works by constructing a PBQP
// problem representing the register allocation problem under consideration,
// solving this using a PBQP solver, and mapping the solution back to a
// register assignment. If any variables are selected for spilling then spill
-// code is inserted and the process repeated.
+// code is inserted and the process repeated.
//
// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
// for register allocation. For more information on PBQP for register
-// allocation see the following papers:
+// allocation, see the following papers:
//
// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
// PBQP. In Proceedings of the 7th Joint Modular Languages Conference
// architectures. In Proceedings of the Joint Conference on Languages,
// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
// NY, USA, 139-148.
-//
-// Author: Lang Hames
-// Email: lhames@gmail.com
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "regalloc"
-#include "PBQP.h"
+#include "PBQP/HeuristicSolver.h"
+#include "PBQP/Graph.h"
+#include "PBQP/Heuristics/Briggs.h"
#include "VirtRegMap.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/RegAllocRegistry.h"
-#include "llvm/CodeGen/RegisterCoalescer.h"
+#include "VirtRegRewriter.h"
+#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegAllocRegistry.h"
+#include "llvm/CodeGen/RegisterCoalescer.h"
#include "llvm/Support/Debug.h"
-#include <memory>
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include <limits>
#include <map>
+#include <memory>
#include <set>
#include <vector>
-#include <limits>
using namespace llvm;
static RegisterRegAlloc
registerPBQPRepAlloc("pbqp", "PBQP register allocator",
- createPBQPRegisterAllocator);
+ llvm::createPBQPRegisterAllocator);
+
+static cl::opt<bool>
+pbqpCoalescing("pbqp-coalescing",
+ cl::desc("Attempt coalescing during PBQP register allocation."),
+ cl::init(false), cl::Hidden);
namespace {
- //!
- //! PBQP based allocators solve the register allocation problem by mapping
- //! register allocation problems to Partitioned Boolean Quadratic
- //! Programming problems.
- class VISIBILITY_HIDDEN PBQPRegAlloc : public MachineFunctionPass {
+ ///
+ /// PBQP based allocators solve the register allocation problem by mapping
+ /// register allocation problems to Partitioned Boolean Quadratic
+ /// Programming problems.
+ class PBQPRegAlloc : public MachineFunctionPass {
public:
static char ID;
-
- //! Construct a PBQP register allocator.
- PBQPRegAlloc() : MachineFunctionPass((intptr_t)&ID) {}
- //! Return the pass name.
- virtual const char* getPassName() const throw() {
+ /// Construct a PBQP register allocator.
+ PBQPRegAlloc() : MachineFunctionPass(&ID) {}
+
+ /// Return the pass name.
+ virtual const char* getPassName() const {
return "PBQP Register Allocator";
}
- //! PBQP analysis usage.
+ /// PBQP analysis usage.
virtual void getAnalysisUsage(AnalysisUsage &au) const {
+ au.addRequired<SlotIndexes>();
+ au.addPreserved<SlotIndexes>();
au.addRequired<LiveIntervals>();
- au.addRequiredTransitive<RegisterCoalescer>();
+ //au.addRequiredID(SplitCriticalEdgesID);
+ au.addRequired<RegisterCoalescer>();
+ au.addRequired<CalculateSpillWeights>();
au.addRequired<LiveStacks>();
au.addPreserved<LiveStacks>();
au.addRequired<MachineLoopInfo>();
au.addPreserved<MachineLoopInfo>();
+ au.addRequired<VirtRegMap>();
MachineFunctionPass::getAnalysisUsage(au);
}
- //! Perform register allocation
+ /// Perform register allocation
virtual bool runOnMachineFunction(MachineFunction &MF);
private:
typedef std::vector<AllowedSet> AllowedSetMap;
typedef std::set<unsigned> RegSet;
typedef std::pair<unsigned, unsigned> RegPair;
- typedef std::map<RegPair, PBQPNum> CoalesceMap;
+ typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
typedef std::set<LiveInterval*> LiveIntervalSet;
+ typedef std::vector<PBQP::Graph::NodeItr> NodeVector;
+
MachineFunction *mf;
const TargetMachine *tm;
const TargetRegisterInfo *tri;
AllowedSetMap allowedSets;
LiveIntervalSet vregIntervalsToAlloc,
emptyVRegIntervals;
+ NodeVector problemNodes;
+
-
- //! Builds a PBQP cost vector.
+ /// Builds a PBQP cost vector.
template <typename RegContainer>
- PBQPVector* buildCostVector(unsigned vReg,
- const RegContainer &allowed,
- const CoalesceMap &cealesces,
- PBQPNum spillCost) const;
-
- //! \brief Builds a PBQP interference matrix.
- //!
- //! @return Either a pointer to a non-zero PBQP matrix representing the
- //! allocation option costs, or a null pointer for a zero matrix.
- //!
- //! Expects allowed sets for two interfering LiveIntervals. These allowed
- //! sets should contain only allocable registers from the LiveInterval's
- //! register class, with any interfering pre-colored registers removed.
+ PBQP::Vector buildCostVector(unsigned vReg,
+ const RegContainer &allowed,
+ const CoalesceMap &cealesces,
+ PBQP::PBQPNum spillCost) const;
+
+ /// \brief Builds a PBQP interference matrix.
+ ///
+ /// @return Either a pointer to a non-zero PBQP matrix representing the
+ /// allocation option costs, or a null pointer for a zero matrix.
+ ///
+ /// Expects allowed sets for two interfering LiveIntervals. These allowed
+ /// sets should contain only allocable registers from the LiveInterval's
+ /// register class, with any interfering pre-colored registers removed.
template <typename RegContainer>
- PBQPMatrix* buildInterferenceMatrix(const RegContainer &allowed1,
- const RegContainer &allowed2) const;
-
- //!
- //! Expects allowed sets for two potentially coalescable LiveIntervals,
- //! and an estimated benefit due to coalescing. The allowed sets should
- //! contain only allocable registers from the LiveInterval's register
- //! classes, with any interfering pre-colored registers removed.
+ PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1,
+ const RegContainer &allowed2) const;
+
+ ///
+ /// Expects allowed sets for two potentially coalescable LiveIntervals,
+ /// and an estimated benefit due to coalescing. The allowed sets should
+ /// contain only allocable registers from the LiveInterval's register
+ /// classes, with any interfering pre-colored registers removed.
template <typename RegContainer>
- PBQPMatrix* buildCoalescingMatrix(const RegContainer &allowed1,
- const RegContainer &allowed2,
- PBQPNum cBenefit) const;
-
- //! \brief Finds coalescing opportunities and returns them as a map.
- //!
- //! Any entries in the map are guaranteed coalescable, even if their
- //! corresponding live intervals overlap.
+ PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1,
+ const RegContainer &allowed2,
+ PBQP::PBQPNum cBenefit) const;
+
+ /// \brief Finds coalescing opportunities and returns them as a map.
+ ///
+ /// Any entries in the map are guaranteed coalescable, even if their
+ /// corresponding live intervals overlap.
CoalesceMap findCoalesces();
- //! \brief Finds the initial set of vreg intervals to allocate.
+ /// \brief Finds the initial set of vreg intervals to allocate.
void findVRegIntervalsToAlloc();
- //! \brief Constructs a PBQP problem representation of the register
- //! allocation problem for this function.
- //!
- //! @return a PBQP solver object for the register allocation problem.
- pbqp* constructPBQPProblem();
+ /// \brief Constructs a PBQP problem representation of the register
+ /// allocation problem for this function.
+ ///
+ /// @return a PBQP solver object for the register allocation problem.
+ PBQP::Graph constructPBQPProblem();
- //! \brief Adds a stack interval if the given live interval has been
- //! spilled. Used to support stack slot coloring.
- void addStackInterval(const LiveInterval *spilled, float &weight);
+ /// \brief Adds a stack interval if the given live interval has been
+ /// spilled. Used to support stack slot coloring.
+ void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);
- //! \brief Given a solved PBQP problem maps this solution back to a register
- //! assignment.
- bool mapPBQPToRegAlloc(pbqp *problem);
+ /// \brief Given a solved PBQP problem maps this solution back to a register
+ /// assignment.
+ bool mapPBQPToRegAlloc(const PBQP::Solution &solution);
- //! \brief Postprocessing before final spilling. Sets basic block "live in"
- //! variables.
+ /// \brief Postprocessing before final spilling. Sets basic block "live in"
+ /// variables.
void finalizeAlloc() const;
};
template <typename RegContainer>
-PBQPVector* PBQPRegAlloc::buildCostVector(unsigned vReg,
- const RegContainer &allowed,
- const CoalesceMap &coalesces,
- PBQPNum spillCost) const {
+PBQP::Vector PBQPRegAlloc::buildCostVector(unsigned vReg,
+ const RegContainer &allowed,
+ const CoalesceMap &coalesces,
+ PBQP::PBQPNum spillCost) const {
typedef typename RegContainer::const_iterator AllowedItr;
// Allocate vector. Additional element (0th) used for spill option
- PBQPVector *v = new PBQPVector(allowed.size() + 1);
+ PBQP::Vector v(allowed.size() + 1, 0);
- (*v)[0] = spillCost;
+ v[0] = spillCost;
// Iterate over the allowed registers inserting coalesce benefits if there
// are any.
// No coalesce - on to the next preg.
if (cmItr == coalesces.end())
continue;
-
- // We have a coalesce - insert the benefit.
- (*v)[ai + 1] = -cmItr->second;
+
+ // We have a coalesce - insert the benefit.
+ v[ai + 1] = -cmItr->second;
}
return v;
}
template <typename RegContainer>
-PBQPMatrix* PBQPRegAlloc::buildInterferenceMatrix(
+PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix(
const RegContainer &allowed1, const RegContainer &allowed2) const {
typedef typename RegContainer::const_iterator RegContainerIterator;
// that the spill option (element 0,0) has zero cost, since we can allocate
// both intervals to memory safely (the cost for each individual allocation
// to memory is accounted for by the cost vectors for each live interval).
- PBQPMatrix *m = new PBQPMatrix(allowed1.size() + 1, allowed2.size() + 1);
-
+ PBQP::Matrix *m =
+ new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
+
// Assume this is a zero matrix until proven otherwise. Zero matrices occur
// between interfering live ranges with non-overlapping register sets (e.g.
// non-overlapping reg classes, or disjoint sets of allowed regs within the
// Row index. Starts at 1, since the 0th row is for the spill option, which
// is always zero.
- unsigned ri = 1;
+ unsigned ri = 1;
- // Iterate over allowed sets, insert infinities where required.
+ // Iterate over allowed sets, insert infinities where required.
for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
a1Itr != a1End; ++a1Itr) {
unsigned reg2 = *a2Itr;
// If the row/column regs are identical or alias insert an infinity.
- if ((reg1 == reg2) || tri->areAliases(reg1, reg2)) {
- (*m)[ri][ci] = std::numeric_limits<PBQPNum>::infinity();
+ if (tri->regsOverlap(reg1, reg2)) {
+ (*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity();
isZeroMatrix = false;
}
}
template <typename RegContainer>
-PBQPMatrix* PBQPRegAlloc::buildCoalescingMatrix(
+PBQP::Matrix* PBQPRegAlloc::buildCoalescingMatrix(
const RegContainer &allowed1, const RegContainer &allowed2,
- PBQPNum cBenefit) const {
+ PBQP::PBQPNum cBenefit) const {
typedef typename RegContainer::const_iterator RegContainerIterator;
// for the LiveIntervals which are (potentially) to be coalesced. The amount
// -cBenefit will be placed in any element representing the same register
// for both intervals.
- PBQPMatrix *m = new PBQPMatrix(allowed1.size() + 1, allowed2.size() + 1);
+ PBQP::Matrix *m =
+ new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
// Reset costs to zero.
m->reset(0);
// If the row and column represent the same register insert a beneficial
// cost to preference this allocation - it would allow us to eliminate a
- // move instruction.
+ // move instruction.
if (reg1 == *a2Itr) {
(*m)[ri][ci] = -cBenefit;
isZeroMatrix = false;
typedef MachineFunction::const_iterator MFIterator;
typedef MachineBasicBlock::const_iterator MBBIterator;
typedef LiveInterval::const_vni_iterator VNIIterator;
-
+
CoalesceMap coalescesFound;
// To find coalesces we need to iterate over the function looking for
iItr != iEnd; ++iItr) {
const MachineInstr *instr = &*iItr;
- unsigned srcReg, dstReg;
+ unsigned srcReg, dstReg, srcSubReg, dstSubReg;
// If this isn't a copy then continue to the next instruction.
- if (!tii->isMoveInstr(*instr, srcReg, dstReg))
+ if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg))
continue;
// If the registers are already the same our job is nice and easy.
// If both registers are physical then we can't coalesce.
if (srcRegIsPhysical && dstRegIsPhysical)
continue;
-
+
// If it's a copy that includes a virtual register but the source and
// destination classes differ then we can't coalesce, so continue with
// the next instruction.
// We also need any physical regs to be allocable, coalescing with
// a non-allocable register is invalid.
if (srcRegIsPhysical) {
- if (std::find(srcRegClass->allocation_order_begin(*mf),
- srcRegClass->allocation_order_end(*mf), srcReg) ==
- srcRegClass->allocation_order_end(*mf))
+ if (std::find(dstRegClass->allocation_order_begin(*mf),
+ dstRegClass->allocation_order_end(*mf), srcReg) ==
+ dstRegClass->allocation_order_end(*mf))
continue;
}
if (dstRegIsPhysical) {
- if (std::find(dstRegClass->allocation_order_begin(*mf),
- dstRegClass->allocation_order_end(*mf), dstReg) ==
- dstRegClass->allocation_order_end(*mf))
+ if (std::find(srcRegClass->allocation_order_begin(*mf),
+ srcRegClass->allocation_order_end(*mf), dstReg) ==
+ srcRegClass->allocation_order_end(*mf))
continue;
}
// If we've made it here we have a copy with compatible register classes.
- // We can probably coalesce, but we need to consider overlap.
+ // We can probably coalesce, but we need to consider overlap.
const LiveInterval *srcLI = &lis->getInterval(srcReg),
*dstLI = &lis->getInterval(dstReg);
bool badDef = false;
// Test all defs of the source range.
- for (VNIIterator
+ for (VNIIterator
vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end();
vniItr != vniEnd; ++vniItr) {
+ // If we find a poorly defined def we err on the side of caution.
+ if (!(*vniItr)->def.isValid()) {
+ badDef = true;
+ break;
+ }
+
// If we find a def that kills the coalescing opportunity then
// record it and break from the loop.
if (dstLI->liveAt((*vniItr)->def)) {
// If we have a bad def give up, continue to the next instruction.
if (badDef)
continue;
-
+
// Otherwise test definitions of the destination range.
for (VNIIterator
vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end();
vniItr != vniEnd; ++vniItr) {
-
+
// We want to make sure we skip the copy instruction itself.
- if ((*vniItr)->copy == instr)
+ if ((*vniItr)->getCopy() == instr)
continue;
+ if (!(*vniItr)->def.isValid()) {
+ badDef = true;
+ break;
+ }
+
if (srcLI->liveAt((*vniItr)->def)) {
badDef = true;
break;
}
}
-
+
// As before a bad def we give up and continue to the next instr.
if (badDef)
continue;
// We're good to go with the coalesce.
float cBenefit = powf(10.0f, loopInfo->getLoopDepth(mbb)) / 5.0;
-
+
coalescesFound[RegPair(srcReg, dstReg)] = cBenefit;
coalescesFound[RegPair(dstReg, srcReg)] = cBenefit;
}
}
}
-pbqp* PBQPRegAlloc::constructPBQPProblem() {
+PBQP::Graph PBQPRegAlloc::constructPBQPProblem() {
typedef std::vector<const LiveInterval*> LIVector;
typedef std::vector<unsigned> RegVector;
// Iterate over vreg intervals, construct live interval <-> node number
// mappings.
- for (LiveIntervalSet::const_iterator
+ for (LiveIntervalSet::const_iterator
itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end();
itr != end; ++itr) {
const LiveInterval *li = *itr;
}
// Get the set of potential coalesces.
- CoalesceMap coalesces(findCoalesces());
+ CoalesceMap coalesces;
+
+ if (pbqpCoalescing) {
+ coalesces = findCoalesces();
+ }
// Construct a PBQP solver for this problem
- pbqp *solver = alloc_pbqp(vregIntervalsToAlloc.size());
+ PBQP::Graph problem;
+ problemNodes.resize(vregIntervalsToAlloc.size());
// Resize allowedSets container appropriately.
allowedSets.resize(vregIntervalsToAlloc.size());
// Grab pointers to the interval and its register class.
const LiveInterval *li = node2LI[node];
const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
-
+
// Start by assuming all allocable registers in the class are allowed...
RegVector liAllowed(liRC->allocation_order_begin(*mf),
liRC->allocation_order_end(*mf));
// Remove the overlapping reg...
RegVector::iterator eraseItr =
std::find(liAllowed.begin(), liAllowed.end(), pReg);
-
+
if (eraseItr != liAllowed.end())
liAllowed.erase(eraseItr);
for (; *aliasItr != 0; ++aliasItr) {
RegVector::iterator eraseItr =
std::find(liAllowed.begin(), liAllowed.end(), *aliasItr);
-
+
if (eraseItr != liAllowed.end()) {
liAllowed.erase(eraseItr);
}
// Set the spill cost to the interval weight, or epsilon if the
// interval weight is zero
- PBQPNum spillCost = (li->weight != 0.0) ?
- li->weight : std::numeric_limits<PBQPNum>::min();
+ PBQP::PBQPNum spillCost = (li->weight != 0.0) ?
+ li->weight : std::numeric_limits<PBQP::PBQPNum>::min();
// Build a cost vector for this interval.
- add_pbqp_nodecosts(solver, node,
- buildCostVector(li->reg, allowedSets[node], coalesces,
- spillCost));
+ problemNodes[node] =
+ problem.addNode(
+ buildCostVector(li->reg, allowedSets[node], coalesces, spillCost));
}
CoalesceMap::const_iterator cmItr =
coalesces.find(RegPair(li->reg, li2->reg));
- PBQPMatrix *m = 0;
+ PBQP::Matrix *m = 0;
if (cmItr != coalesces.end()) {
m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2],
else if (li->overlaps(*li2)) {
m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]);
}
-
+
if (m != 0) {
- add_pbqp_edgecosts(solver, node1, node2, m);
+ problem.addEdge(problemNodes[node1],
+ problemNodes[node2],
+ *m);
+
delete m;
}
}
}
+ assert(problem.getNumNodes() == allowedSets.size());
+/*
+ std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, "
+ << problem.getNumEdges() << " edges.\n";
+
+ problem.printDot(std::cerr);
+*/
// We're done, PBQP problem constructed - return it.
- return solver;
+ return problem;
}
-void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, float &weight) {
+void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled,
+ MachineRegisterInfo* mri) {
int stackSlot = vrm->getStackSlot(spilled->reg);
-
- if (stackSlot == VirtRegMap::NO_STACK_SLOT)
+
+ if (stackSlot == VirtRegMap::NO_STACK_SLOT)
return;
- LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot);
- stackInterval.weight += weight;
+ const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
+ LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC);
VNInfo *vni;
if (stackInterval.getNumValNums() != 0)
vni = stackInterval.getValNumInfo(0);
else
- vni = stackInterval.getNextValue(-0U, 0, lss->getVNInfoAllocator());
+ vni = stackInterval.getNextValue(
+ SlotIndex(), 0, false, lss->getVNInfoAllocator());
LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
stackInterval.MergeRangesInAsValue(rhsInterval, vni);
}
-bool PBQPRegAlloc::mapPBQPToRegAlloc(pbqp *problem) {
-
+bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
+
// Set to true if we have any spills
bool anotherRoundNeeded = false;
// Clear the existing allocation.
vrm->clearAllVirt();
-
+
// Iterate over the nodes mapping the PBQP solution to a register assignment.
for (unsigned node = 0; node < node2LI.size(); ++node) {
unsigned virtReg = node2LI[node]->reg,
- allocSelection = get_pbqp_solution(problem, node);
+ allocSelection = solution.getSelection(problemNodes[node]);
+
// If the PBQP solution is non-zero it's a physical register...
if (allocSelection != 0) {
// Get the physical reg, subtracting 1 to account for the spill option.
unsigned physReg = allowedSets[node][allocSelection - 1];
- DOUT << "VREG " << virtReg << " -> " << tri->getName(physReg) << "\n";
+ DEBUG(dbgs() << "VREG " << virtReg << " -> "
+ << tri->getName(physReg) << "\n");
assert(physReg != 0);
// of allocation
vregIntervalsToAlloc.erase(&lis->getInterval(virtReg));
- float ssWeight;
-
// Insert spill ranges for this live range
const LiveInterval *spillInterval = node2LI[node];
double oldSpillWeight = spillInterval->weight;
SmallVector<LiveInterval*, 8> spillIs;
std::vector<LiveInterval*> newSpills =
- lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm,
- ssWeight);
- addStackInterval(spillInterval, ssWeight);
+ lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
+ addStackInterval(spillInterval, mri);
- DOUT << "VREG " << virtReg << " -> SPILLED (Cost: "
- << oldSpillWeight << ", New vregs: ";
+ (void) oldSpillWeight;
+ DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Cost: "
+ << oldSpillWeight << ", New vregs: ");
// Copy any newly inserted live intervals into the list of regs to
// allocate.
assert(!(*itr)->empty() && "Empty spill range.");
- DOUT << (*itr)->reg << " ";
+ DEBUG(dbgs() << (*itr)->reg << " ");
vregIntervalsToAlloc.insert(*itr);
}
- DOUT << ")\n";
+ DEBUG(dbgs() << ")\n");
// We need another round if spill intervals were added.
anotherRoundNeeded |= !newSpills.empty();
// First allocate registers for the empty intervals.
for (LiveIntervalSet::const_iterator
- itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
+ itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
itr != end; ++itr) {
- LiveInterval *li = *itr;
+ LiveInterval *li = *itr;
- unsigned physReg = li->preference;
+ unsigned physReg = vrm->getRegAllocPref(li->reg);
if (physReg == 0) {
const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
- physReg = *liRC->allocation_order_begin(*mf);
+ physReg = *liRC->allocation_order_begin(*mf);
}
-
- vrm->assignVirt2Phys(li->reg, physReg);
+
+ vrm->assignVirt2Phys(li->reg, physReg);
}
-
+
// Finally iterate over the basic blocks to compute and set the live-in sets.
SmallVector<MachineBasicBlock*, 8> liveInMBBs;
MachineBasicBlock *entryMBB = &*mf->begin();
const LiveInterval *li = liItr->second;
unsigned reg = 0;
-
+
// Get the physical register for this interval
if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
reg = li->reg;
continue;
}
+ if (reg == 0) {
+ // Filter out zero regs - they're for intervals that were spilled.
+ continue;
+ }
+
// Iterate over the ranges of the current interval...
for (LRIterator lrItr = li->begin(), lrEnd = li->end();
lrItr != lrEnd; ++lrItr) {
-
+
// Find the set of basic blocks which this range is live into...
if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
// And add the physreg for this interval to their live-in sets.
}
}
}
-
+
}
bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) {
tm = &mf->getTarget();
tri = tm->getRegisterInfo();
tii = tm->getInstrInfo();
- mri = &mf->getRegInfo();
+ mri = &mf->getRegInfo();
lis = &getAnalysis<LiveIntervals>();
lss = &getAnalysis<LiveStacks>();
loopInfo = &getAnalysis<MachineLoopInfo>();
- std::auto_ptr<VirtRegMap> vrmAutoPtr(new VirtRegMap(*mf));
- vrm = vrmAutoPtr.get();
+ vrm = &getAnalysis<VirtRegMap>();
- DOUT << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n";
+ DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n");
// Allocator main loop:
- //
+ //
// * Map current regalloc problem to a PBQP problem
// * Solve the PBQP problem
// * Map the solution back to a register allocation
// * Spill if necessary
- //
+ //
// This process is continued till no more spills are generated.
// Find the vreg intervals in need of allocation.
findVRegIntervalsToAlloc();
-
- // If there aren't any then we're done here.
- if (vregIntervalsToAlloc.empty() && emptyVRegIntervals.empty())
- return true;
// If there are non-empty intervals allocate them using pbqp.
if (!vregIntervalsToAlloc.empty()) {
unsigned round = 0;
while (!pbqpAllocComplete) {
- DOUT << " PBQP Regalloc round " << round << ":\n";
+ DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
- pbqp *problem = constructPBQPProblem();
-
- solve_pbqp(problem);
-
- pbqpAllocComplete = mapPBQPToRegAlloc(problem);
+ PBQP::Graph problem = constructPBQPProblem();
+ PBQP::Solution solution =
+ PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(problem);
- free_pbqp(problem);
+ pbqpAllocComplete = mapPBQPToRegAlloc(solution);
++round;
}
li2Node.clear();
node2LI.clear();
allowedSets.clear();
+ problemNodes.clear();
+
+ DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
- DOUT << "Post alloc VirtRegMap:\n" << *vrm << "\n";
+ // Run rewriter
+ std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
- // Run spiller
- std::auto_ptr<Spiller> spiller(createSpiller());
- spiller->runOnMachineFunction(*mf, *vrm);
+ rewriter->runOnMachineFunction(*mf, *vrm, lis);
- return true;
+ return true;
}
FunctionPass* llvm::createPBQPRegisterAllocator() {
projects / oota-llvm.git / blobdiff