#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "Support/Debug.h"
-#include "Support/Statistic.h"
-#include <iostream>
-
-namespace llvm {
+#include "llvm/Support/Debug.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/STLExtras.h"
+using namespace llvm;
namespace {
- Statistic<> NumSpilled ("ra-simple", "Number of registers spilled");
- Statistic<> NumReloaded("ra-simple", "Number of registers reloaded");
+ Statistic<> NumStores("ra-simple", "Number of stores added");
+ Statistic<> NumLoads ("ra-simple", "Number of loads added");
class RegAllocSimple : public MachineFunctionPass {
MachineFunction *MF;
const TargetMachine *TM;
const MRegisterInfo *RegInfo;
+ bool *PhysRegsEverUsed;
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
/// Moves value from memory into that register
unsigned reloadVirtReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I, unsigned VirtReg);
+ MachineBasicBlock::iterator I, unsigned VirtReg);
/// Saves reg value on the stack (maps virtual register to stack value)
- void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
+ void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg);
};
return I->second; // Already has space allocated?
// Allocate a new stack object for this spill location...
- int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC);
+ int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
+ RC->getAlignment());
// Assign the slot...
StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
assert(RI+regIdx != RE && "Not enough registers!");
unsigned PhysReg = *(RI+regIdx);
- if (!RegsUsed[PhysReg])
+ if (!RegsUsed[PhysReg]) {
+ PhysRegsEverUsed[PhysReg] = true;
return PhysReg;
+ }
}
}
unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
unsigned VirtReg) {
const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC);
unsigned PhysReg = getFreeReg(VirtReg);
// Add move instruction(s)
- ++NumReloaded;
- RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ ++NumLoads;
+ RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
return PhysReg;
}
void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
- ++NumSpilled;
- RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ ++NumStores;
+ RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
}
RegsUsed.resize(RegInfo->getNumRegs());
- // a preliminary pass that will invalidate any registers that
- // are used by the instruction (including implicit uses)
+ // This is a preliminary pass that will invalidate any registers that are
+ // used by the instruction (including implicit uses).
unsigned Opcode = MI->getOpcode();
- const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
- const unsigned *Regs = Desc.ImplicitUses;
- while (*Regs)
- RegsUsed[*Regs++] = true;
+ const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
+ const unsigned *Regs;
+ for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
+ RegsUsed[*Regs] = true;
- Regs = Desc.ImplicitDefs;
- while (*Regs)
- RegsUsed[*Regs++] = true;
+ for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
+ RegsUsed[*Regs] = true;
+ PhysRegsEverUsed[*Regs] = true;
+ }
- // Loop over uses, move from memory into registers
+ // Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i);
- if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
+ if (op.isRegister() && op.getReg() &&
+ MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";
- MI->print(std::cerr, *TM));
+ MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
- if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
+ if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
+ physReg = getFreeReg(virtualReg);
+ } else {
// must be same register number as the first operand
// This maps a = b + c into b += c, and saves b into a's spot
assert(MI->getOperand(1).isRegister() &&
"Two address instruction invalid!");
physReg = MI->getOperand(1).getReg();
- } else {
- physReg = getFreeReg(virtualReg);
+ spillVirtReg(MBB, next(MI), virtualReg, physReg);
+ MI->getOperand(1).setDef();
+ MI->RemoveOperand(0);
+ break; // This is the last operand to process
}
- ++MI;
- spillVirtReg(MBB, MI, virtualReg, physReg);
- --MI;
+ spillVirtReg(MBB, next(MI), virtualReg, physReg);
} else {
physReg = reloadVirtReg(MBB, MI, virtualReg);
Virt2PhysRegMap[virtualReg] = physReg;
TM = &MF->getTarget();
RegInfo = TM->getRegisterInfo();
+ PhysRegsEverUsed = new bool[RegInfo->getNumRegs()];
+ std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false);
+ Fn.setUsedPhysRegs(PhysRegsEverUsed);
+
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB)
return true;
}
-FunctionPass *createSimpleRegisterAllocator() {
+FunctionPass *llvm::createSimpleRegisterAllocator() {
return new RegAllocSimple();
}
-
-} // End llvm namespace
projects / oota-llvm.git / blobdiff