When extending a liveinterval by commuting, don't throw away the live ranges that...

[oota-llvm.git] / lib / CodeGen / RegAllocSimple.cpp

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index f9923a51f2eb6c9bb084453bb28e8c8f5d757c2b..081edd8d5eb8b0a5f8b3b2c8bbe36e4b3687a44e 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -18,8 +18,8 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -27,6 +27,7 @@
 #include "llvm/Support/Compiler.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
+#include <map>
 using namespace llvm;
 
 STATISTIC(NumStores, "Number of stores added");
@@ -44,7 +45,7 @@ namespace {
   private:
     MachineFunction *MF;
     const TargetMachine *TM;
-    const MRegisterInfo *RegInfo;
+    const TargetRegisterInfo *TRI;
 
     // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
     // these values are spilled
@@ -119,7 +120,7 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
 }
 
 unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
-  const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg);
+  const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg);
   TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
   TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
 
@@ -129,7 +130,7 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
     unsigned PhysReg = *(RI+regIdx);
 
     if (!RegsUsed[PhysReg]) {
-      MF->setPhysRegUsed(PhysReg);
+      MF->getRegInfo().setPhysRegUsed(PhysReg);
       return PhysReg;
     }
   }
@@ -138,25 +139,28 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
 unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator I,
                                        unsigned VirtReg) {
-  const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
+  const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
   int FrameIdx = getStackSpaceFor(VirtReg, RC);
   unsigned PhysReg = getFreeReg(VirtReg);
 
   // Add move instruction(s)
   ++NumLoads;
-  RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+  const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+  TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
   return PhysReg;
 }
 
 void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I,
                                   unsigned VirtReg, unsigned PhysReg) {
-  const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
+  const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
+  const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+  
   int FrameIdx = getStackSpaceFor(VirtReg, RC);
 
   // Add move instruction(s)
   ++NumStores;
-  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
+  TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
 }
 
 
@@ -166,12 +170,11 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     // Made to combat the incorrect allocation of r2 = add r1, r1
     std::map<unsigned, unsigned> Virt2PhysRegMap;
 
-    RegsUsed.resize(RegInfo->getNumRegs());
+    RegsUsed.resize(TRI->getNumRegs());
 
     // This is a preliminary pass that will invalidate any registers that are
     // used by the instruction (including implicit uses).
-    unsigned Opcode = MI->getOpcode();
-    const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
+    const TargetInstrDesc &Desc = MI->getDesc();
     const unsigned *Regs;
     if (Desc.ImplicitUses) {
       for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
@@ -181,7 +184,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     if (Desc.ImplicitDefs) {
       for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
         RegsUsed[*Regs] = true;
-        MF->setPhysRegUsed(*Regs);
+        MF->getRegInfo().setPhysRegUsed(*Regs);
       }
     }
 
@@ -190,7 +193,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
       MachineOperand &op = MI->getOperand(i);
 
       if (op.isRegister() && op.getReg() &&
-          MRegisterInfo::isVirtualRegister(op.getReg())) {
+          TargetRegisterInfo::isVirtualRegister(op.getReg())) {
         unsigned virtualReg = (unsigned) op.getReg();
         DOUT << "op: " << op << "\n";
         DOUT << "\t inst[" << i << "]: ";
@@ -201,7 +204,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
           if (op.isDef()) {
-            int TiedOp = MI->getInstrDescriptor()->findTiedToSrcOperand(i);
+            int TiedOp = Desc.findTiedToSrcOperand(i);
             if (TiedOp == -1) {
               physReg = getFreeReg(virtualReg);
             } else {
@@ -237,7 +240,7 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
   DOUT << "Machine Function\n";
   MF = &Fn;
   TM = &MF->getTarget();
-  RegInfo = TM->getRegisterInfo();
+  TRI = TM->getRegisterInfo();
 
   // Loop over all of the basic blocks, eliminating virtual register references
   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();