#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
+#include <map>
using namespace llvm;
STATISTIC(NumStores, "Number of stores added");
private:
MachineFunction *MF;
const TargetMachine *TM;
- const MRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
// Add move instruction(s)
++NumLoads;
- MRI->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+ TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
++NumStores;
- MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
+ TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
}
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- RegsUsed.resize(MRI->getNumRegs());
+ RegsUsed.resize(TRI->getNumRegs());
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
- unsigned Opcode = MI->getOpcode();
- const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
+ const TargetInstrDesc &Desc = MI->getDesc();
const unsigned *Regs;
if (Desc.ImplicitUses) {
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
MachineOperand &op = MI->getOperand(i);
if (op.isRegister() && op.getReg() &&
- MRegisterInfo::isVirtualRegister(op.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg();
DOUT << "op: " << op << "\n";
DOUT << "\t inst[" << i << "]: ";
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
- int TiedOp = MI->getInstrDescriptor()->findTiedToSrcOperand(i);
+ int TiedOp = Desc.findTiedToSrcOperand(i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {
DOUT << "Machine Function\n";
MF = &Fn;
TM = &MF->getTarget();
- MRI = TM->getRegisterInfo();
+ TRI = TM->getRegisterInfo();
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();