Finegrainify namespacification

[oota-llvm.git] / lib / CodeGen / RegAllocSimple.cpp

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index a40ec64077bdf523e157a629ac86aac2c08647d1..1b7f5471b423e415471dd23167e31fe494f50623 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -24,13 +24,13 @@
 #include "llvm/Target/TargetMachine.h"
 #include "Support/Debug.h"
 #include "Support/Statistic.h"
+#include "Support/STLExtras.h"
 #include <iostream>
-
-namespace llvm {
+using namespace llvm;
 
 namespace {
-  Statistic<> NumSpilled ("ra-simple", "Number of registers spilled");
-  Statistic<> NumReloaded("ra-simple", "Number of registers reloaded");
+  Statistic<> NumStores("ra-simple", "Number of stores added");
+  Statistic<> NumLoads ("ra-simple", "Number of loads added");
 
   class RegAllocSimple : public MachineFunctionPass {
     MachineFunction *MF;
@@ -79,10 +79,10 @@ namespace {
 
     /// Moves value from memory into that register
     unsigned reloadVirtReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator &I, unsigned VirtReg);
+                           MachineBasicBlock::iterator I, unsigned VirtReg);
 
     /// Saves reg value on the stack (maps virtual register to stack value)
-    void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
+    void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                       unsigned VirtReg, unsigned PhysReg);
   };
 
@@ -124,26 +124,26 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
 }
 
 unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
-                                       MachineBasicBlock::iterator &I,
+                                       MachineBasicBlock::iterator I,
                                        unsigned VirtReg) {
   const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
   int FrameIdx = getStackSpaceFor(VirtReg, RC);
   unsigned PhysReg = getFreeReg(VirtReg);
 
   // Add move instruction(s)
-  ++NumReloaded;
+  ++NumLoads;
   RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
   return PhysReg;
 }
 
 void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
-                                  MachineBasicBlock::iterator &I,
+                                  MachineBasicBlock::iterator I,
                                   unsigned VirtReg, unsigned PhysReg) {
   const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
   int FrameIdx = getStackSpaceFor(VirtReg, RC);
 
   // Add move instruction(s)
-  ++NumSpilled;
+  ++NumStores;
   RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
 }
 
@@ -154,7 +154,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     // Made to combat the incorrect allocation of r2 = add r1, r1
     std::map<unsigned, unsigned> Virt2PhysRegMap;
 
-    RegsUsed.resize(MRegisterInfo::FirstVirtualRegister);
+    RegsUsed.resize(RegInfo->getNumRegs());
     
     // a preliminary pass that will invalidate any registers that
     // are used by the instruction (including implicit uses)
@@ -172,8 +172,9 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
       MachineOperand &op = MI->getOperand(i);
       
-      if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
-        unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
+      if (op.isRegister() && op.getReg() &&
+          MRegisterInfo::isVirtualRegister(op.getReg())) {
+        unsigned virtualReg = (unsigned) op.getReg();
         DEBUG(std::cerr << "op: " << op << "\n");
         DEBUG(std::cerr << "\t inst[" << i << "]: ";
               MI->print(std::cerr, *TM));
@@ -183,21 +184,23 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
           if (op.isDef()) {
-            if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
+            if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) {
+              physReg = getFreeReg(virtualReg);
+            } else {
               // must be same register number as the first operand
               // This maps a = b + c into b += c, and saves b into a's spot
               assert(MI->getOperand(1).isRegister()  &&
-                     MI->getOperand(1).getAllocatedRegNum() &&
+                     MI->getOperand(1).getReg() &&
                      MI->getOperand(1).isUse() &&
                      "Two address instruction invalid!");
 
-              physReg = MI->getOperand(1).getAllocatedRegNum();
-            } else {
-              physReg = getFreeReg(virtualReg);
+              physReg = MI->getOperand(1).getReg();
+              spillVirtReg(MBB, next(MI), virtualReg, physReg);
+              MI->getOperand(1).setDef();
+              MI->RemoveOperand(0);
+              break; // This is the last operand to process
             }
-            ++MI;
-            spillVirtReg(MBB, MI, virtualReg, physReg);
-            --MI;
+            spillVirtReg(MBB, next(MI), virtualReg, physReg);
           } else {
             physReg = reloadVirtReg(MBB, MI, virtualReg);
             Virt2PhysRegMap[virtualReg] = physReg;
@@ -205,7 +208,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
         }
         MI->SetMachineOperandReg(i, physReg);
         DEBUG(std::cerr << "virt: " << virtualReg << 
-              ", phys: " << op.getAllocatedRegNum() << "\n");
+              ", phys: " << op.getReg() << "\n");
       }
     }
     RegClassIdx.clear();
@@ -231,8 +234,6 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
   return true;
 }
 
-FunctionPass *createSimpleRegisterAllocator() {
+FunctionPass *llvm::createSimpleRegisterAllocator() {
   return new RegAllocSimple();
 }
-
-} // End llvm namespace