It is obvious that this has never been used for outputing more than a single

[oota-llvm.git] / lib / CodeGen / RegAllocSimple.cpp

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 57d678b02f0711a0988298055022f31f8002665d..44f37c61e859ebc1773924800183b4a907b03083 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -1,4 +1,11 @@
 //===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
 //
 // This file implements a simple register allocator. *Very* simple: It immediate
 // spills every value right after it is computed, and it reloads all used
@@ -19,6 +26,8 @@
 #include "Support/Statistic.h"
 #include <iostream>
 
+namespace llvm {
+
 namespace {
   Statistic<> NumSpilled ("ra-simple", "Number of registers spilled");
   Statistic<> NumReloaded("ra-simple", "Number of registers reloaded");
@@ -153,13 +162,13 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     // are used by the instruction (including implicit uses)
     unsigned Opcode = MI->getOpcode();
     const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
-    if (const unsigned *Regs = Desc.ImplicitUses)
-      while (*Regs)
-       RegsUsed[*Regs++] = true;
+    const unsigned *Regs = Desc.ImplicitUses;
+    while (*Regs)
+      RegsUsed[*Regs++] = true;
     
-    if (const unsigned *Regs = Desc.ImplicitDefs)
-      while (*Regs)
-       RegsUsed[*Regs++] = true;
+    Regs = Desc.ImplicitDefs;
+    while (*Regs)
+      RegsUsed[*Regs++] = true;
     
     // Loop over uses, move from memory into registers
     for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
@@ -175,13 +184,13 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
         // register in any given instruction
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
-          if (op.opIsDefOnly() || op.opIsDefAndUse()) {
+          if (op.isDef()) {
             if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
               // must be same register number as the first operand
               // This maps a = b + c into b += c, and saves b into a's spot
               assert(MI->getOperand(1).isRegister()  &&
                      MI->getOperand(1).getAllocatedRegNum() &&
-                     MI->getOperand(1).opIsUse() &&
+                     MI->getOperand(1).isUse() &&
                      "Two address instruction invalid!");
 
               physReg = MI->getOperand(1).getAllocatedRegNum();
@@ -227,3 +236,5 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
 FunctionPass *createSimpleRegisterAllocator() {
   return new RegAllocSimple();
 }
+
+} // End llvm namespace