namespace {
static RegisterRegAlloc
- simpleRegAlloc("simple", " simple register allocator",
+ simpleRegAlloc("simple", "simple register allocator",
createSimpleRegisterAllocator);
class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
public:
static char ID;
- RegAllocSimple() : MachineFunctionPass((intptr_t)&ID) {}
+ RegAllocSimple() : MachineFunctionPass(&ID) {}
private:
MachineFunction *MF;
const TargetMachine *TM;
unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg);
TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
+#ifndef NDEBUG
TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
+#endif
while (1) {
unsigned regIdx = RegClassIdx[RC]++;
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isRegister() && MO.getReg() &&
+ if (MO.isReg() && MO.getReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned virtualReg = (unsigned) MO.getReg();
DOUT << "op: " << MO << "\n";
// must be same register number as the source operand that is
// tied to. This maps a = b + c into b = b + c, and saves b into
// a's spot.
- assert(MI->getOperand(TiedOp).isRegister() &&
+ assert(MI->getOperand(TiedOp).isReg() &&
MI->getOperand(TiedOp).getReg() &&
MI->getOperand(TiedOp).isUse() &&
"Two address instruction invalid!");