Don't use a random type for the select condition,

[oota-llvm.git] / lib / CodeGen / RegAllocSimple.cpp

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 87b09a2a0dceaf6d753b38df0b0ffb68378032df..7dc98904abcc9b8625b41b8dd337ae91e4600a2b 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -35,7 +35,7 @@ STATISTIC(NumLoads , "Number of loads added");
 
 namespace {
   static RegisterRegAlloc
-    simpleRegAlloc("simple", "  simple register allocator",
+    simpleRegAlloc("simple", "simple register allocator",
                    createSimpleRegisterAllocator);
 
   class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
@@ -190,7 +190,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
       MachineOperand &MO = MI->getOperand(i);
 
-      if (MO.isRegister() && MO.getReg() &&
+      if (MO.isReg() && MO.getReg() &&
           TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
         unsigned virtualReg = (unsigned) MO.getReg();
         DOUT << "op: " << MO << "\n";
@@ -209,7 +209,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
               // must be same register number as the source operand that is 
               // tied to. This maps a = b + c into b = b + c, and saves b into
               // a's spot.
-              assert(MI->getOperand(TiedOp).isRegister()  &&
+              assert(MI->getOperand(TiedOp).isReg()  &&
                      MI->getOperand(TiedOp).getReg() &&
                      MI->getOperand(TiedOp).isUse() &&
                      "Two address instruction invalid!");