#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
+#include <iostream>
using namespace llvm;
namespace {
- Statistic<> NumStores("ra-simple", "Number of stores added");
- Statistic<> NumLoads ("ra-simple", "Number of loads added");
+ static Statistic<> NumStores("ra-simple", "Number of stores added");
+ static Statistic<> NumLoads ("ra-simple", "Number of loads added");
- class RegAllocSimple : public MachineFunctionPass {
+ static RegisterRegAlloc
+ simpleRegAlloc("simple", " simple register allocator",
+ createSimpleRegisterAllocator);
+
+ class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
MachineFunction *MF;
const TargetMachine *TM;
const MRegisterInfo *RegInfo;
unsigned Opcode = MI->getOpcode();
const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
const unsigned *Regs;
- for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
- RegsUsed[*Regs] = true;
+ if (Desc.ImplicitUses) {
+ for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
+ RegsUsed[*Regs] = true;
+ }
- for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
- RegsUsed[*Regs] = true;
- PhysRegsEverUsed[*Regs] = true;
+ if (Desc.ImplicitDefs) {
+ for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
+ RegsUsed[*Regs] = true;
+ PhysRegsEverUsed[*Regs] = true;
+ }
}
// Loop over uses, move from memory into registers.
physReg = getFreeReg(virtualReg);
} else {
// must be same register number as the first operand
- // This maps a = b + c into b += c, and saves b into a's spot
+ // This maps a = b + c into b = b + c, and saves b into a's spot.
assert(MI->getOperand(1).isRegister() &&
MI->getOperand(1).getReg() &&
MI->getOperand(1).isUse() &&
"Two address instruction invalid!");
physReg = MI->getOperand(1).getReg();
- spillVirtReg(MBB, next(MI), virtualReg, physReg);
- MI->getOperand(1).setDef();
- MI->RemoveOperand(0);
- break; // This is the last operand to process
}
spillVirtReg(MBB, next(MI), virtualReg, physReg);
} else {
Virt2PhysRegMap[virtualReg] = physReg;
}
}
- MI->SetMachineOperandReg(i, physReg);
+ MI->getOperand(i).setReg(physReg);
DEBUG(std::cerr << "virt: " << virtualReg <<
", phys: " << op.getReg() << "\n");
}