//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file implements a simple register allocator. *Very* simple: It immediate
// spills every value right after it is computed, and it reloads all used
//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "regalloc"
+#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
-#include "llvm/CodeGen/FunctionFrameInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "Support/Statistic.h"
-#include <iostream>
+#include "llvm/Support/Debug.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/STLExtras.h"
+using namespace llvm;
namespace {
- Statistic<> NumSpilled ("ra-simple", "Number of registers spilled");
- Statistic<> NumReloaded("ra-simple", "Number of registers reloaded");
+ Statistic<> NumStores("ra-simple", "Number of stores added");
+ Statistic<> NumLoads ("ra-simple", "Number of loads added");
class RegAllocSimple : public MachineFunctionPass {
MachineFunction *MF;
/// runOnMachineFunction - Register allocate the whole function
bool runOnMachineFunction(MachineFunction &Fn);
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequiredID(PHIEliminationID); // Eliminate PHI nodes
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
private:
/// AllocateBasicBlock - Register allocate the specified basic block.
void AllocateBasicBlock(MachineBasicBlock &MBB);
- /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
- /// in predecessor basic blocks.
- void EliminatePHINodes(MachineBasicBlock &MBB);
-
/// getStackSpaceFor - This returns the offset of the specified virtual
- /// register on the stack, allocating space if neccesary.
+ /// register on the stack, allocating space if necessary.
int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
/// Given a virtual register, return a compatible physical register that is
/// Moves value from memory into that register
unsigned reloadVirtReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I, unsigned VirtReg);
+ MachineBasicBlock::iterator I, unsigned VirtReg);
/// Saves reg value on the stack (maps virtual register to stack value)
- void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
+ void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg);
};
return I->second; // Already has space allocated?
// Allocate a new stack object for this spill location...
- int FrameIdx =
- MF->getFrameInfo()->CreateStackObject(RC->getSize(), RC->getAlignment());
+ int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
+ RC->getAlignment());
// Assign the slot...
StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
}
unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
unsigned VirtReg) {
const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC);
unsigned PhysReg = getFreeReg(VirtReg);
// Add move instruction(s)
- ++NumReloaded;
- RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ ++NumLoads;
+ RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
return PhysReg;
}
void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
- ++NumSpilled;
- RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
-}
-
-
-/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
-/// predecessor basic blocks.
-///
-void RegAllocSimple::EliminatePHINodes(MachineBasicBlock &MBB) {
- const MachineInstrInfo &MII = TM->getInstrInfo();
-
- while (MBB.front()->getOpcode() == MachineInstrInfo::PHI) {
- MachineInstr *MI = MBB.front();
- // Unlink the PHI node from the basic block... but don't delete the PHI yet
- MBB.erase(MBB.begin());
-
- DEBUG(std::cerr << "num ops: " << MI->getNumOperands() << "\n");
- assert(MI->getOperand(0).isVirtualRegister() &&
- "PHI node doesn't write virt reg?");
-
- unsigned virtualReg = MI->getOperand(0).getAllocatedRegNum();
-
- for (int i = MI->getNumOperands() - 1; i >= 2; i-=2) {
- MachineOperand &opVal = MI->getOperand(i-1);
-
- // Get the MachineBasicBlock equivalent of the BasicBlock that is the
- // source path the phi
- MachineBasicBlock &opBlock = *MI->getOperand(i).getMachineBasicBlock();
-
- // Check to make sure we haven't already emitted the copy for this block.
- // This can happen because PHI nodes may have multiple entries for the
- // same basic block. It doesn't matter which entry we use though, because
- // all incoming values are guaranteed to be the same for a particular bb.
- //
- // Note that this is N^2 in the number of phi node entries, but since the
- // # of entries is tiny, this is not a problem.
- //
- bool HaveNotEmitted = true;
- for (int op = MI->getNumOperands() - 1; op != i; op -= 2)
- if (&opBlock == MI->getOperand(op).getMachineBasicBlock()) {
- HaveNotEmitted = false;
- break;
- }
-
- if (HaveNotEmitted) {
- MachineBasicBlock::iterator opI = opBlock.end();
- MachineInstr *opMI = *--opI;
-
- // must backtrack over ALL the branches in the previous block
- while (MII.isBranch(opMI->getOpcode()) && opI != opBlock.begin())
- opMI = *--opI;
-
- // move back to the first branch instruction so new instructions
- // are inserted right in front of it and not in front of a non-branch
- //
- if (!MII.isBranch(opMI->getOpcode()))
- ++opI;
-
- const TargetRegisterClass *RC =
- MF->getSSARegMap()->getRegClass(virtualReg);
-
- assert(opVal.isVirtualRegister() &&
- "Machine PHI Operands must all be virtual registers!");
- RegInfo->copyRegToReg(opBlock, opI, virtualReg, opVal.getReg(), RC);
- }
- }
-
- // really delete the PHI instruction now!
- delete MI;
- }
+ ++NumStores;
+ RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
}
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction
- for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
+ for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- MachineInstr *MI = *I;
-
- RegsUsed.resize(MRegisterInfo::FirstVirtualRegister);
+ RegsUsed.resize(RegInfo->getNumRegs());
// a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
- if (const unsigned *Regs = Desc.ImplicitUses)
- while (*Regs)
- RegsUsed[*Regs++] = true;
+ const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
+ const unsigned *Regs = Desc.ImplicitUses;
+ while (*Regs)
+ RegsUsed[*Regs++] = true;
- if (const unsigned *Regs = Desc.ImplicitDefs)
- while (*Regs)
- RegsUsed[*Regs++] = true;
+ Regs = Desc.ImplicitDefs;
+ while (*Regs)
+ RegsUsed[*Regs++] = true;
// Loop over uses, move from memory into registers
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i);
- if (op.isVirtualRegister()) {
- unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
+ if (op.isRegister() && op.getReg() &&
+ MRegisterInfo::isVirtualRegister(op.getReg())) {
+ unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";
- MI->print(std::cerr, *TM));
+ MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
- if (op.opIsDef()) {
- if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
+ if (op.isDef()) {
+ if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
+ physReg = getFreeReg(virtualReg);
+ } else {
// must be same register number as the first operand
// This maps a = b + c into b += c, and saves b into a's spot
assert(MI->getOperand(1).isRegister() &&
- MI->getOperand(1).getAllocatedRegNum() &&
- MI->getOperand(1).opIsUse() &&
+ MI->getOperand(1).getReg() &&
+ MI->getOperand(1).isUse() &&
"Two address instruction invalid!");
- physReg = MI->getOperand(1).getAllocatedRegNum();
- } else {
- physReg = getFreeReg(virtualReg);
+ physReg = MI->getOperand(1).getReg();
+ spillVirtReg(MBB, next(MI), virtualReg, physReg);
+ MI->getOperand(1).setDef();
+ MI->RemoveOperand(0);
+ break; // This is the last operand to process
}
- ++I;
- spillVirtReg(MBB, I, virtualReg, physReg);
- --I;
+ spillVirtReg(MBB, next(MI), virtualReg, physReg);
} else {
- physReg = reloadVirtReg(MBB, I, virtualReg);
+ physReg = reloadVirtReg(MBB, MI, virtualReg);
Virt2PhysRegMap[virtualReg] = physReg;
}
}
MI->SetMachineOperandReg(i, physReg);
DEBUG(std::cerr << "virt: " << virtualReg <<
- ", phys: " << op.getAllocatedRegNum() << "\n");
+ ", phys: " << op.getReg() << "\n");
}
}
RegClassIdx.clear();
TM = &MF->getTarget();
RegInfo = TM->getRegisterInfo();
- // First pass: eliminate PHI instructions by inserting copies into predecessor
- // blocks.
- for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
- MBB != MBBe; ++MBB)
- EliminatePHINodes(*MBB);
-
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB)
return true;
}
-Pass *createSimpleRegisterAllocator() {
+FunctionPass *llvm::createSimpleRegisterAllocator() {
return new RegAllocSimple();
}
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