Allow hbd to be bugpointable on darwin by fixing common and linkonce codegen

[oota-llvm.git] / lib / CodeGen / RegAllocSimple.cpp

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index a210790b8dd77f0313d02be7fae97e4c9ac01c23..ba05bd3830974725cea8e2679598fa2edb6a06b9 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -22,13 +22,14 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
-#include "Support/Debug.h"
-#include "Support/Statistic.h"
-#include <iostream>
+#include "llvm/Support/Debug.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/STLExtras.h"
+using namespace llvm;
 
 namespace {
-  Statistic<> NumSpilled ("ra-simple", "Number of registers spilled");
-  Statistic<> NumReloaded("ra-simple", "Number of registers reloaded");
+  Statistic<> NumStores("ra-simple", "Number of stores added");
+  Statistic<> NumLoads ("ra-simple", "Number of loads added");
 
   class RegAllocSimple : public MachineFunctionPass {
     MachineFunction *MF;
@@ -77,10 +78,10 @@ namespace {
 
     /// Moves value from memory into that register
     unsigned reloadVirtReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator &I, unsigned VirtReg);
+                           MachineBasicBlock::iterator I, unsigned VirtReg);
 
     /// Saves reg value on the stack (maps virtual register to stack value)
-    void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
+    void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                       unsigned VirtReg, unsigned PhysReg);
   };
 
@@ -98,7 +99,8 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
     return I->second;          // Already has space allocated?
 
   // Allocate a new stack object for this spill location...
-  int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC);
+  int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
+                                                       RC->getAlignment());
   
   // Assign the slot...
   StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
@@ -122,44 +124,42 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
 }
 
 unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
-                                       MachineBasicBlock::iterator &I,
+                                       MachineBasicBlock::iterator I,
                                        unsigned VirtReg) {
   const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
   int FrameIdx = getStackSpaceFor(VirtReg, RC);
   unsigned PhysReg = getFreeReg(VirtReg);
 
   // Add move instruction(s)
-  ++NumReloaded;
-  RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+  ++NumLoads;
+  RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
   return PhysReg;
 }
 
 void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
-                                  MachineBasicBlock::iterator &I,
+                                  MachineBasicBlock::iterator I,
                                   unsigned VirtReg, unsigned PhysReg) {
   const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
   int FrameIdx = getStackSpaceFor(VirtReg, RC);
 
   // Add move instruction(s)
-  ++NumSpilled;
-  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+  ++NumStores;
+  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
 }
 
 
 void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
   // loop over each instruction
-  for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
+  for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
     // Made to combat the incorrect allocation of r2 = add r1, r1
     std::map<unsigned, unsigned> Virt2PhysRegMap;
 
-    MachineInstr *MI = *I;
-
-    RegsUsed.resize(MRegisterInfo::FirstVirtualRegister);
+    RegsUsed.resize(RegInfo->getNumRegs());
     
     // a preliminary pass that will invalidate any registers that
     // are used by the instruction (including implicit uses)
     unsigned Opcode = MI->getOpcode();
-    const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
+    const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
     const unsigned *Regs = Desc.ImplicitUses;
     while (*Regs)
       RegsUsed[*Regs++] = true;
@@ -172,40 +172,43 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
       MachineOperand &op = MI->getOperand(i);
       
-      if (op.isVirtualRegister()) {
-        unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
+      if (op.isRegister() && op.getReg() &&
+          MRegisterInfo::isVirtualRegister(op.getReg())) {
+        unsigned virtualReg = (unsigned) op.getReg();
         DEBUG(std::cerr << "op: " << op << "\n");
         DEBUG(std::cerr << "\t inst[" << i << "]: ";
-              MI->print(std::cerr, *TM));
+              MI->print(std::cerr, TM));
         
         // make sure the same virtual register maps to the same physical
         // register in any given instruction
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
-          if (op.opIsDefOnly() || op.opIsDefAndUse()) {
-            if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
+          if (op.isDef()) {
+            if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
+              physReg = getFreeReg(virtualReg);
+            } else {
               // must be same register number as the first operand
               // This maps a = b + c into b += c, and saves b into a's spot
               assert(MI->getOperand(1).isRegister()  &&
-                     MI->getOperand(1).getAllocatedRegNum() &&
-                     MI->getOperand(1).opIsUse() &&
+                     MI->getOperand(1).getReg() &&
+                     MI->getOperand(1).isUse() &&
                      "Two address instruction invalid!");
 
-              physReg = MI->getOperand(1).getAllocatedRegNum();
-            } else {
-              physReg = getFreeReg(virtualReg);
+              physReg = MI->getOperand(1).getReg();
+              spillVirtReg(MBB, next(MI), virtualReg, physReg);
+              MI->getOperand(1).setDef();
+              MI->RemoveOperand(0);
+              break; // This is the last operand to process
             }
-            ++I;
-            spillVirtReg(MBB, I, virtualReg, physReg);
-            --I;
+            spillVirtReg(MBB, next(MI), virtualReg, physReg);
           } else {
-            physReg = reloadVirtReg(MBB, I, virtualReg);
+            physReg = reloadVirtReg(MBB, MI, virtualReg);
             Virt2PhysRegMap[virtualReg] = physReg;
           }
         }
         MI->SetMachineOperandReg(i, physReg);
         DEBUG(std::cerr << "virt: " << virtualReg << 
-              ", phys: " << op.getAllocatedRegNum() << "\n");
+              ", phys: " << op.getReg() << "\n");
       }
     }
     RegClassIdx.clear();
@@ -231,6 +234,6 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
   return true;
 }
 
-FunctionPass *createSimpleRegisterAllocator() {
+FunctionPass *llvm::createSimpleRegisterAllocator() {
   return new RegAllocSimple();
 }