Fix a bug in my previous patch, grabbing the shift amount width from the

[oota-llvm.git] / lib / CodeGen / RegAllocSimple.cpp

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index b28e21aaf61b708ecfa7f604bd21b63cd0be07c6..e632e3599ac65b42fb116aed3efb51dfeafc8a0a 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -27,13 +27,12 @@
 #include "llvm/Support/Compiler.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
-#include <iostream>
 using namespace llvm;
 
-namespace {
-  static Statistic<> NumStores("ra-simple", "Number of stores added");
-  static Statistic<> NumLoads ("ra-simple", "Number of loads added");
+STATISTIC(NumStores, "Number of stores added");
+STATISTIC(NumLoads , "Number of loads added");
 
+namespace {
   static RegisterRegAlloc
     simpleRegAlloc("simple", "  simple register allocator",
                    createSimpleRegisterAllocator);
@@ -190,30 +189,28 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
       if (op.isRegister() && op.getReg() &&
           MRegisterInfo::isVirtualRegister(op.getReg())) {
         unsigned virtualReg = (unsigned) op.getReg();
-        DEBUG(std::cerr << "op: " << op << "\n");
-        DEBUG(std::cerr << "\t inst[" << i << "]: ";
-              MI->print(std::cerr, TM));
+        DOUT << "op: " << op << "\n";
+        DOUT << "\t inst[" << i << "]: ";
+        DEBUG(MI->print(*cerr.stream(), TM));
 
         // make sure the same virtual register maps to the same physical
         // register in any given instruction
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
           if (op.isDef()) {
-            if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
+            int TiedOp = MI->getInstrDescriptor()->findTiedToSrcOperand(i);
+            if (TiedOp == -1) {
               physReg = getFreeReg(virtualReg);
             } else {
-              // must be same register number as the first operand
-              // This maps a = b + c into b += c, and saves b into a's spot
-              assert(MI->getOperand(1).isRegister()  &&
-                     MI->getOperand(1).getReg() &&
-                     MI->getOperand(1).isUse() &&
+              // must be same register number as the source operand that is 
+              // tied to. This maps a = b + c into b = b + c, and saves b into
+              // a's spot.
+              assert(MI->getOperand(TiedOp).isRegister()  &&
+                     MI->getOperand(TiedOp).getReg() &&
+                     MI->getOperand(TiedOp).isUse() &&
                      "Two address instruction invalid!");
 
-              physReg = MI->getOperand(1).getReg();
-              spillVirtReg(MBB, next(MI), virtualReg, physReg);
-              MI->getOperand(1).setDef();
-              MI->RemoveOperand(0);
-              break; // This is the last operand to process
+              physReg = MI->getOperand(TiedOp).getReg();
             }
             spillVirtReg(MBB, next(MI), virtualReg, physReg);
           } else {
@@ -222,8 +219,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
           }
         }
         MI->getOperand(i).setReg(physReg);
-        DEBUG(std::cerr << "virt: " << virtualReg <<
-              ", phys: " << op.getReg() << "\n");
+        DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
       }
     }
     RegClassIdx.clear();
@@ -235,7 +231,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
 /// runOnMachineFunction - Register allocate the whole function
 ///
 bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
-  DEBUG(std::cerr << "Machine Function " << "\n");
+  DOUT << "Machine Function\n";
   MF = &Fn;
   TM = &MF->getTarget();
   RegInfo = TM->getRegisterInfo();