Fix a bug in my previous patch, grabbing the shift amount width from the
[oota-llvm.git] / lib / CodeGen / RegAllocSimple.cpp
index f08b039b82e8dc1e47461769831e042dc667172b..e632e3599ac65b42fb116aed3efb51dfeafc8a0a 100644 (file)
 #include "llvm/Support/Compiler.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
-#include <iostream>
 using namespace llvm;
 
-namespace {
-  static Statistic<> NumStores("ra-simple", "Number of stores added");
-  static Statistic<> NumLoads ("ra-simple", "Number of loads added");
+STATISTIC(NumStores, "Number of stores added");
+STATISTIC(NumLoads , "Number of loads added");
 
+namespace {
   static RegisterRegAlloc
     simpleRegAlloc("simple", "  simple register allocator",
                    createSimpleRegisterAllocator);
@@ -192,15 +191,14 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
         unsigned virtualReg = (unsigned) op.getReg();
         DOUT << "op: " << op << "\n";
         DOUT << "\t inst[" << i << "]: ";
-        DEBUG(MI->print(std::cerr, TM));
+        DEBUG(MI->print(*cerr.stream(), TM));
 
         // make sure the same virtual register maps to the same physical
         // register in any given instruction
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
           if (op.isDef()) {
-            int TiedOp = TM->getInstrInfo()
-              ->findTiedToSrcOperand(MI->getOpcode(), i);
+            int TiedOp = MI->getInstrDescriptor()->findTiedToSrcOperand(i);
             if (TiedOp == -1) {
               physReg = getFreeReg(virtualReg);
             } else {