#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
-#include <iostream>
using namespace llvm;
-namespace {
- static Statistic<> NumStores("ra-simple", "Number of stores added");
- static Statistic<> NumLoads ("ra-simple", "Number of loads added");
+STATISTIC(NumStores, "Number of stores added");
+STATISTIC(NumLoads , "Number of loads added");
+namespace {
static RegisterRegAlloc
simpleRegAlloc("simple", " simple register allocator",
createSimpleRegisterAllocator);
if (op.isRegister() && op.getReg() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg();
- DEBUG(std::cerr << "op: " << op << "\n");
- DEBUG(std::cerr << "\t inst[" << i << "]: ";
- MI->print(std::cerr, TM));
+ DOUT << "op: " << op << "\n";
+ DOUT << "\t inst[" << i << "]: ";
+ DEBUG(MI->print(*cerr.stream(), TM));
// make sure the same virtual register maps to the same physical
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
- int TiedOp = TM->getInstrInfo()
- ->getTiedToSrcOperand(MI->getOpcode(), i);
+ int TiedOp = MI->getInstrDescriptor()->findTiedToSrcOperand(i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {
}
}
MI->getOperand(i).setReg(physReg);
- DEBUG(std::cerr << "virt: " << virtualReg <<
- ", phys: " << op.getReg() << "\n");
+ DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
}
}
RegClassIdx.clear();
/// runOnMachineFunction - Register allocate the whole function
///
bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
- DEBUG(std::cerr << "Machine Function " << "\n");
+ DOUT << "Machine Function\n";
MF = &Fn;
TM = &MF->getTarget();
RegInfo = TM->getRegisterInfo();