improve "cannot yet select" errors a trivial amount: now

[oota-llvm.git] / lib / CodeGen / RegisterCoalescer.cpp

diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp
index b18f0957b62728ead2533eb5d15ea5889024719c..407559a211a0a7de65521795985d0856b0312e33 100644 (file)
--- a/lib/CodeGen/RegisterCoalescer.cpp
+++ b/lib/CodeGen/RegisterCoalescer.cpp
@@ -24,7 +24,8 @@
 using namespace llvm;
 
 // Register the RegisterCoalescer interface, providing a nice name to refer to.
-static RegisterAnalysisGroup<RegisterCoalescer> Z("Register Coalescer");
+INITIALIZE_ANALYSIS_GROUP(RegisterCoalescer, "Register Coalescer", 
+                          SimpleRegisterCoalescing)
 char RegisterCoalescer::ID = 0;
 
 // RegisterCoalescer destructor: DO NOT move this to the header file
@@ -44,26 +45,25 @@ unsigned CoalescerPair::compose(unsigned a, unsigned b) const {
 bool CoalescerPair::isMoveInstr(const MachineInstr *MI,
                                 unsigned &Src, unsigned &Dst,
                                 unsigned &SrcSub, unsigned &DstSub) const {
-  if (MI->isExtractSubreg()) {
+  if (MI->isCopy()) {
     Dst = MI->getOperand(0).getReg();
     DstSub = MI->getOperand(0).getSubReg();
     Src = MI->getOperand(1).getReg();
-    SrcSub = compose(MI->getOperand(1).getSubReg(), MI->getOperand(2).getImm());
-  } else if (MI->isInsertSubreg() || MI->isSubregToReg()) {
+    SrcSub = MI->getOperand(1).getSubReg();
+  } else if (MI->isSubregToReg()) {
     Dst = MI->getOperand(0).getReg();
     DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());
     Src = MI->getOperand(2).getReg();
     SrcSub = MI->getOperand(2).getSubReg();
-  } else if (!tii_.isMoveInstr(*MI, Src, Dst, SrcSub, DstSub)) {
+  } else
     return false;
-  }
   return true;
 }
 
 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
   srcReg_ = dstReg_ = subIdx_ = 0;
   newRC_ = 0;
-  flipped_ = false;
+  flipped_ = crossClass_ = false;
 
   unsigned Src, Dst, SrcSub, DstSub;
   if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub))
@@ -100,11 +100,19 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
   } else {
     // Both registers are virtual.
 
-    // Identical sub to sub.
-    if (SrcSub == DstSub)
+    // Both registers have subreg indices.
+    if (SrcSub && DstSub) {
+      // For now we only handle the case of identical indices in commensurate
+      // registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg
+      // FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg.
+      if (SrcSub != DstSub)
+        return false;
+      const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
+      const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
+      if (!getCommonSubClass(DstRC, SrcRC))
+        return false;
       SrcSub = DstSub = 0;
-    else if (SrcSub && DstSub)
-      return false; // FIXME: Qreg:ssub_3 + Dreg:ssub_1 => QReg:dsub_1 + Dreg.
+    }
 
     // There can be no SrcSub.
     if (SrcSub) {
@@ -124,6 +132,7 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
       newRC_ = getCommonSubClass(DstRC, SrcRC);
     if (!newRC_)
       return false;
+    crossClass_ = newRC_ != DstRC || newRC_ != SrcRC;
   }
   // Check our invariants
   assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");