RegInfo->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(MBBI);
- RegInfo->eliminateFrameIndex(II, this);
+ RegInfo->eliminateFrameIndex(II, 0, this);
setUsed(ScavengedReg);
ScavengedReg = 0;
ScavengedRC = NULL;
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse())
+ if (!MO.isRegister() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
if (!isUsed(Reg)) {
// Register has been scavenged. Restore it!
if (Reg != ScavengedReg)
- assert(false);
+ assert(false && "Using an undefined register!");
else
restoreScavengedReg();
}
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ if (!MO.isRegister() || !MO.isDef())
continue;
unsigned Reg = MO.getReg();
// If it's dead upon def, then it is now free.
}
// Skip two-address destination operand.
if (TID->findTiedToSrcOperand(i) != -1) {
- assert(isUsed(Reg));
+ assert(isUsed(Reg) && "Using an undefined register!");
continue;
}
- assert(isUnused(Reg) || isReserved(Reg));
+ assert((isUnused(Reg) || isReserved(Reg)) &&
+ "Re-defining a live register!");
setUsed(Reg);
}
}
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ if (!MO.isRegister() || !MO.isDef())
continue;
// Skip two-address destination operand.
if (TID->findTiedToSrcOperand(i) != -1)
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse())
+ if (!MO.isRegister() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
I = next(I);
while (I != MBB->end()) {
Dist++;
- if (I->findRegisterUseOperand(Reg) != -1)
+ if (I->findRegisterUseOperandIdx(Reg) != -1)
return Dist;
I = next(I);
}
}
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
- MachineBasicBlock::iterator I) {
+ MachineBasicBlock::iterator I,
+ int SPAdj) {
assert(ScavengingFrameIndex >= 0 &&
"Cannot scavenge a register without an emergency spill slot!");
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
- if (MO.isReg())
+ if (MO.isRegister())
Candidates.reset(MO.getReg());
}
RegInfo->loadRegFromStackSlot(*MBB, I, ScavengedReg,
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(I);
- RegInfo->eliminateFrameIndex(II, this);
+ RegInfo->eliminateFrameIndex(II, SPAdj, this);
}
RegInfo->storeRegToStackSlot(*MBB, I, SReg, ScavengingFrameIndex, RC);
MachineBasicBlock::iterator II = prior(I);
- RegInfo->eliminateFrameIndex(II, this);
+ RegInfo->eliminateFrameIndex(II, SPAdj, this);
ScavengedReg = SReg;
ScavengedRC = RC;