//===----------------------------------------------------------------------===//
//
// This file implements the machine register scavenger. It can provide
-// information such as unused register at any point in a machine basic block.
-// It also provides a mechanism to make registers availbale by evicting them
-// to spill slots.
+// information, such as unused registers, at any point in a machine basic block.
+// It also provides a mechanism to make registers available by evicting them to
+// spill slots.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
+/// RedefinesSuperRegPart - Return true if the specified register is redefining
+/// part of a super-register.
+static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
+ const TargetRegisterInfo *TRI) {
+ bool SeenSuperUse = false;
+ bool SeenSuperDef = false;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isRegister())
+ continue;
+ if (TRI->isSuperRegister(SubReg, MO.getReg())) {
+ if (MO.isUse())
+ SeenSuperUse = true;
+ else if (MO.isImplicit())
+ SeenSuperDef = true;
+ }
+ }
+
+ return SeenSuperDef && SeenSuperUse;
+}
+
+static bool RedefinesSuperRegPart(const MachineInstr *MI,
+ const MachineOperand &MO,
+ const TargetRegisterInfo *TRI) {
+ assert(MO.isRegister() && MO.isDef() && "Not a register def!");
+ return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
+}
+
/// setUsed - Set the register and its sub-registers as being used.
-void RegScavenger::setUsed(unsigned Reg) {
+void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
RegsAvailable.reset(Reg);
+ ImplicitDefed[Reg] = ImpDef;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs)
+ unsigned SubReg = *SubRegs; ++SubRegs) {
RegsAvailable.reset(SubReg);
+ ImplicitDefed[SubReg] = ImpDef;
+ }
}
/// setUnused - Set the register and its sub-registers as being unused.
-void RegScavenger::setUnused(unsigned Reg) {
+void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
RegsAvailable.set(Reg);
+ ImplicitDefed.reset(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
- RegsAvailable.set(SubReg);
+ if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
+ RegsAvailable.set(SubReg);
+ ImplicitDefed.reset(SubReg);
+ }
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
- const MachineFunction &MF = *mbb->getParent();
+ MachineFunction &MF = *mbb->getParent();
const TargetMachine &TM = MF.getTarget();
TII = TM.getInstrInfo();
TRI = TM.getRegisterInfo();
+ MRI = &MF.getRegInfo();
assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
"Target changed?");
if (!MBB) {
NumPhysRegs = TRI->getNumRegs();
RegsAvailable.resize(NumPhysRegs);
+ ImplicitDefed.resize(NumPhysRegs);
// Create reserved registers bitvector.
ReservedRegs = TRI->getReservedRegs(MF);
return;
TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
- ScavengingFrameIndex, ScavengedRC);
+ ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(MBBI);
TRI->eliminateFrameIndex(II, 0, this);
setUsed(ScavengedReg);
ScavengedRC = NULL;
}
+/// isLiveInButUnusedBefore - Return true if register is livein the MBB not
+/// not used before it reaches the MI that defines register.
+static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
+ MachineBasicBlock *MBB,
+ const TargetRegisterInfo *TRI,
+ MachineRegisterInfo* MRI) {
+ // First check if register is livein.
+ bool isLiveIn = false;
+ for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
+ E = MBB->livein_end(); I != E; ++I)
+ if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
+ isLiveIn = true;
+ break;
+ }
+ if (!isLiveIn)
+ return false;
+
+ // Is there any use of it before the specified MI?
+ SmallPtrSet<MachineInstr*, 4> UsesInMBB;
+ for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
+ UE = MRI->use_end(); UI != UE; ++UI) {
+ MachineInstr *UseMI = &*UI;
+ if (UseMI->getParent() == MBB)
+ UsesInMBB.insert(UseMI);
+ }
+ if (UsesInMBB.empty())
+ return true;
+
+ for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
+ if (UsesInMBB.count(&*I))
+ return false;
+ return true;
+}
+
void RegScavenger::forward() {
// Move ptr forward.
if (!Tracking) {
if (MO.isKill() && !isReserved(Reg)) {
ChangedRegs.set(Reg);
+ // Mark sub-registers as changed if they aren't defined in the same
+ // instruction.
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
ChangedRegs.set(SubReg);
setUnused(ChangedRegs);
// Process defs.
+ bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
// If it's dead upon def, then it is now free.
if (MO.isDead()) {
- setUnused(Reg);
+ setUnused(Reg, MI);
continue;
}
continue;
}
- assert((isUnused(Reg) || isReserved(Reg)) &&
+ // Skip is this is merely redefining part of a super-register.
+ if (RedefinesSuperRegPart(MI, MO, TRI))
+ continue;
+
+ // Implicit def is allowed to "re-define" any register. Similarly,
+ // implicitly defined registers can be clobbered.
+ assert((isReserved(Reg) || isUnused(Reg) ||
+ IsImpDef || isImplicitlyDefined(Reg) ||
+ isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
"Re-defining a live register!");
- setUsed(Reg);
+ setUsed(Reg, IsImpDef);
}
}
unsigned Reg = MO.getReg();
assert(isUsed(Reg));
if (!isReserved(Reg))
- setUnused(Reg);
+ setUnused(Reg, MI);
}
// Process uses.
projects / oota-llvm.git / blobdiff