Allow targets to custom handle softening of results or operands before trying the...

[oota-llvm.git] / lib / CodeGen / RegisterScavenging.cpp

diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 7d8e3afa7892aed6ef652471e4a1da1d6ab357fd..e1c8f2fe22eeb44a200976ac5492c573b1326a0e 100644 (file)
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -20,6 +20,7 @@
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -56,6 +57,14 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI,
   return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
 }
 
+bool RegScavenger::isSuperRegUsed(unsigned Reg) const {
+  for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
+       unsigned SuperReg = *SuperRegs; ++SuperRegs)
+    if (isUsed(SuperReg))
+      return true;
+  return false;
+}
+
 /// setUsed - Set the register and its sub-registers as being used.
 void RegScavenger::setUsed(unsigned Reg) {
   RegsAvailable.reset(Reg);
@@ -154,6 +163,9 @@ static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
   SmallPtrSet<MachineInstr*, 4> UsesInMBB;
   for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
          UE = MRI->use_end(); UI != UE; ++UI) {
+    MachineOperand &UseMO = UI.getOperand();
+    if (UseMO.isReg() && UseMO.isUndef())
+      continue;
     MachineInstr *UseMI = &*UI;
     if (UseMI->getParent() == MBB)
       UsesInMBB.insert(UseMI);
@@ -187,6 +199,11 @@ void RegScavenger::forward() {
     ScavengeRestore = NULL;
   }
 
+#if 0
+  if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+    return;
+#endif
+
   // Separate register operands into 3 classes: uses, defs, earlyclobbers.
   SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
   SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
@@ -209,7 +226,7 @@ void RegScavenger::forward() {
     const MachineOperand MO = *UseMOs[i].first;
     unsigned Reg = MO.getReg();
 
-    assert(isUsed(Reg) && "Using an undefined register!");
+    assert((MO.isImplicit() || isUsed(Reg)) && "Using an undefined register!");
 
     if (MO.isKill() && !isReserved(Reg)) {
       KillRegs.set(Reg);
@@ -237,6 +254,8 @@ void RegScavenger::forward() {
     unsigned Idx = (i < NumECs)
       ? EarlyClobberMOs[i].second : DefMOs[i-NumECs].second;
     unsigned Reg = MO.getReg();
+    if (MO.isUndef())
+      continue;
 
     // If it's dead upon def, then it is now free.
     if (MO.isDead()) {
@@ -245,7 +264,9 @@ void RegScavenger::forward() {
     }
 
     // Skip two-address destination operand.
-    if (MI->isRegTiedToUseOperand(Idx)) {
+    unsigned UseIdx;
+    if (MI->isRegTiedToUseOperand(Idx, &UseIdx) &&
+        !MI->getOperand(UseIdx).isUndef()) {
       assert(isUsed(Reg) && "Using an undefined register!");
       continue;
     }
@@ -256,7 +277,8 @@ void RegScavenger::forward() {
 
     // Implicit def is allowed to "re-define" any register. Similarly,
     // implicitly defined registers can be clobbered.
-    assert((isReserved(Reg) || isUnused(Reg) ||
+    assert((MO.isImplicit() || isReserved(Reg) || isUnused(Reg) ||
+            isSuperRegUsed(Reg) ||
             isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
            "Re-defining a live register!");
     setUsed(Reg);
@@ -298,6 +320,8 @@ void RegScavenger::backward() {
       ? *DefMOs[i].first : *EarlyClobberMOs[i-NumDefs].first;
     unsigned Idx = (i < NumECs)
       ? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second;
+    if (MO.isUndef())
+      continue;
 
     // Skip two-address destination operand.
     if (MI->isRegTiedToUseOperand(Idx))
@@ -414,7 +438,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
   // Mask off the registers which are not in the TargetRegisterClass.
   BitVector Candidates(NumPhysRegs, false);
   CreateRegClassMask(RC, Candidates);
-  Candidates ^= ReservedRegs;  // Do not include reserved registers.
+  Candidates ^= ReservedRegs & Candidates; // Do not include reserved registers.
 
   // Exclude all the registers being used by the instruction.
   for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
@@ -447,9 +471,14 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
     Reg = Candidates.find_next(Reg);
   }
 
-  if (ScavengedReg != 0) {
-    assert(0 && "Scavenger slot is live, unable to scavenge another register!");
-    abort();
+  assert(ScavengedReg == 0 &&
+         "Scavenger slot is live, unable to scavenge another register!");
+
+  // Make sure SReg is marked as used. It could be considered available if it is
+  // one of the callee saved registers, but hasn't been spilled.
+  if (!isUsed(SReg)) {
+    MBB->addLiveIn(SReg);
+    setUsed(SReg);
   }
 
   // Spill the scavenged register before I.