#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
bool SeenSuperDef = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg())
+ if (!MO.isReg() || MO.isUndef())
continue;
if (TRI->isSuperRegister(SubReg, MO.getReg())) {
if (MO.isUse())
return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
}
+bool RegScavenger::isSuperRegUsed(unsigned Reg) const {
+ for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
+ unsigned SuperReg = *SuperRegs; ++SuperRegs)
+ if (isUsed(SuperReg))
+ return true;
+ return false;
+}
+
/// setUsed - Set the register and its sub-registers as being used.
-void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
+void RegScavenger::setUsed(unsigned Reg) {
RegsAvailable.reset(Reg);
- ImplicitDefed[Reg] = ImpDef;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs) {
+ unsigned SubReg = *SubRegs; ++SubRegs)
RegsAvailable.reset(SubReg);
- ImplicitDefed[SubReg] = ImpDef;
- }
}
/// setUnused - Set the register and its sub-registers as being unused.
void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
RegsAvailable.set(Reg);
- ImplicitDefed.reset(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
- if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
+ if (!RedefinesSuperRegPart(MI, Reg, TRI))
RegsAvailable.set(SubReg);
- ImplicitDefed.reset(SubReg);
- }
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
if (!MBB) {
NumPhysRegs = TRI->getNumRegs();
RegsAvailable.resize(NumPhysRegs);
- ImplicitDefed.resize(NumPhysRegs);
// Create reserved registers bitvector.
ReservedRegs = TRI->getReservedRegs(MF);
MBB = mbb;
ScavengedReg = 0;
ScavengedRC = NULL;
+ ScavengeRestore = NULL;
+ CurrDist = 0;
+ DistanceMap.clear();
// All registers started out unused.
RegsAvailable.set();
}
void RegScavenger::restoreScavengedReg() {
- if (!ScavengedReg)
- return;
-
TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(MBBI);
ScavengedRC = NULL;
}
+#ifndef NDEBUG
/// isLiveInButUnusedBefore - Return true if register is livein the MBB not
/// not used before it reaches the MI that defines register.
static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
SmallPtrSet<MachineInstr*, 4> UsesInMBB;
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
UE = MRI->use_end(); UI != UE; ++UI) {
+ MachineOperand &UseMO = UI.getOperand();
+ if (UseMO.isReg() && UseMO.isUndef())
+ continue;
MachineInstr *UseMI = &*UI;
if (UseMI->getParent() == MBB)
UsesInMBB.insert(UseMI);
return false;
return true;
}
+#endif
void RegScavenger::forward() {
// Move ptr forward.
}
MachineInstr *MI = MBBI;
- const TargetInstrDesc &TID = MI->getDesc();
+ DistanceMap.insert(std::make_pair(MI, CurrDist++));
- // Reaching a terminator instruction. Restore a scavenged register (which
- // must be life out.
- if (TID.isTerminator())
- restoreScavengedReg();
+ if (MI == ScavengeRestore) {
+ ScavengedReg = 0;
+ ScavengedRC = NULL;
+ ScavengeRestore = NULL;
+ }
- bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
+#if 0
+ if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+ return;
+#endif
// Separate register operands into 3 classes: uses, defs, earlyclobbers.
- SmallVector<const MachineOperand*, 4> UseMOs;
- SmallVector<const MachineOperand*, 4> DefMOs;
- SmallVector<const MachineOperand*, 4> EarlyClobberMOs;
+ SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
+ SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
+ SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || MO.getReg() == 0)
+ if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef())
continue;
if (MO.isUse())
- UseMOs.push_back(&MO);
+ UseMOs.push_back(std::make_pair(&MO,i));
else if (MO.isEarlyClobber())
- EarlyClobberMOs.push_back(&MO);
+ EarlyClobberMOs.push_back(std::make_pair(&MO,i));
else
- DefMOs.push_back(&MO);
+ DefMOs.push_back(std::make_pair(&MO,i));
}
// Process uses first.
- BitVector UseRegs(NumPhysRegs);
+ BitVector KillRegs(NumPhysRegs);
for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
- const MachineOperand &MO = *UseMOs[i];
+ const MachineOperand MO = *UseMOs[i].first;
unsigned Reg = MO.getReg();
- if (!isUsed(Reg)) {
- // Register has been scavenged. Restore it!
- if (Reg == ScavengedReg)
- restoreScavengedReg();
- else
- assert(false && "Using an undefined register!");
- }
+ assert((MO.isImplicit() || isUsed(Reg)) && "Using an undefined register!");
if (MO.isKill() && !isReserved(Reg)) {
- UseRegs.set(Reg);
+ KillRegs.set(Reg);
// Mark sub-registers as used.
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
- UseRegs.set(SubReg);
+ KillRegs.set(SubReg);
}
}
// Change states of all registers after all the uses are processed to guard
// against multiple uses.
- setUnused(UseRegs);
+ setUnused(KillRegs);
// Process early clobber defs then process defs. We can have a early clobber
// that is dead, it should not conflict with a def that happens one "slot"
for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
const MachineOperand &MO = (i < NumECs)
- ? *EarlyClobberMOs[i] : *DefMOs[i-NumECs];
+ ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
+ unsigned Idx = (i < NumECs)
+ ? EarlyClobberMOs[i].second : DefMOs[i-NumECs].second;
unsigned Reg = MO.getReg();
+ if (MO.isUndef())
+ continue;
// If it's dead upon def, then it is now free.
if (MO.isDead()) {
}
// Skip two-address destination operand.
- if (TID.findTiedToSrcOperand(i) != -1) {
+ unsigned UseIdx;
+ if (MI->isRegTiedToUseOperand(Idx, &UseIdx) &&
+ !MI->getOperand(UseIdx).isUndef()) {
assert(isUsed(Reg) && "Using an undefined register!");
continue;
}
- // Skip is this is merely redefining part of a super-register.
+ // Skip if this is merely redefining part of a super-register.
if (RedefinesSuperRegPart(MI, MO, TRI))
continue;
// Implicit def is allowed to "re-define" any register. Similarly,
// implicitly defined registers can be clobbered.
- assert((isReserved(Reg) || isUnused(Reg) ||
- IsImpDef || isImplicitlyDefined(Reg) ||
+ assert((MO.isImplicit() || isReserved(Reg) || isUnused(Reg) ||
+ isSuperRegUsed(Reg) ||
isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
"Re-defining a live register!");
- setUsed(Reg, IsImpDef);
+ setUsed(Reg);
}
}
MBBI = prior(MBBI);
MachineInstr *MI = MBBI;
- // Process defs first.
- const TargetInstrDesc &TID = MI->getDesc();
+ DistanceMap.erase(MI);
+ --CurrDist;
+
+ // Separate register operands into 3 classes: uses, defs, earlyclobbers.
+ SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
+ SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
+ SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef())
continue;
+ if (MO.isUse())
+ UseMOs.push_back(std::make_pair(&MO,i));
+ else if (MO.isEarlyClobber())
+ EarlyClobberMOs.push_back(std::make_pair(&MO,i));
+ else
+ DefMOs.push_back(std::make_pair(&MO,i));
+ }
+
+
+ // Process defs first.
+ unsigned NumECs = EarlyClobberMOs.size();
+ unsigned NumDefs = DefMOs.size();
+ for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
+ const MachineOperand &MO = (i < NumDefs)
+ ? *DefMOs[i].first : *EarlyClobberMOs[i-NumDefs].first;
+ unsigned Idx = (i < NumECs)
+ ? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second;
+ if (MO.isUndef())
+ continue;
+
// Skip two-address destination operand.
- if (TID.findTiedToSrcOperand(i) != -1)
+ if (MI->isRegTiedToUseOperand(Idx))
continue;
+
unsigned Reg = MO.getReg();
assert(isUsed(Reg));
if (!isReserved(Reg))
// Process uses.
BitVector UseRegs(NumPhysRegs);
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse())
- continue;
+ for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
+ const MachineOperand MO = *UseMOs[i].first;
unsigned Reg = MO.getReg();
- if (Reg == 0)
- continue;
assert(isUnused(Reg) || isReserved(Reg));
UseRegs.set(Reg);
return (Reg == -1) ? 0 : Reg;
}
-/// calcDistanceToUse - Calculate the distance to the first use of the
+/// findFirstUse - Calculate the distance to the first use of the
/// specified register.
-static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator I, unsigned Reg,
- const TargetRegisterInfo *TRI) {
- unsigned Dist = 0;
- I = next(I);
- while (I != MBB->end()) {
- Dist++;
- if (I->readsRegister(Reg, TRI))
- return Dist;
- I = next(I);
+MachineInstr*
+RegScavenger::findFirstUse(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator I, unsigned Reg,
+ unsigned &Dist) {
+ MachineInstr *UseMI = 0;
+ Dist = ~0U;
+ for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
+ RE = MRI->reg_end(); RI != RE; ++RI) {
+ MachineInstr *UDMI = &*RI;
+ if (UDMI->getParent() != MBB)
+ continue;
+ DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
+ if (DI == DistanceMap.end()) {
+ // If it's not in map, it's below current MI, let's initialize the
+ // map.
+ I = next(I);
+ unsigned Dist = CurrDist + 1;
+ while (I != MBB->end()) {
+ DistanceMap.insert(std::make_pair(I, Dist++));
+ I = next(I);
+ }
+ }
+ DI = DistanceMap.find(UDMI);
+ if (DI->second > CurrDist && DI->second < Dist) {
+ Dist = DI->second;
+ UseMI = UDMI;
+ }
}
- return Dist + 1;
+ return UseMI;
}
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
// Mask off the registers which are not in the TargetRegisterClass.
BitVector Candidates(NumPhysRegs, false);
CreateRegClassMask(RC, Candidates);
- Candidates ^= ReservedRegs; // Do not include reserved registers.
+ Candidates ^= ReservedRegs & Candidates; // Do not include reserved registers.
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
// Find the register whose use is furthest away.
unsigned SReg = 0;
unsigned MaxDist = 0;
+ MachineInstr *MaxUseMI = 0;
int Reg = Candidates.find_first();
while (Reg != -1) {
- unsigned Dist = calcDistanceToUse(MBB, I, Reg, TRI);
+ unsigned Dist;
+ MachineInstr *UseMI = findFirstUse(MBB, I, Reg, Dist);
+ for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
+ unsigned AsDist;
+ MachineInstr *AsUseMI = findFirstUse(MBB, I, *AS, AsDist);
+ if (AsDist < Dist) {
+ Dist = AsDist;
+ UseMI = AsUseMI;
+ }
+ }
if (Dist >= MaxDist) {
MaxDist = Dist;
+ MaxUseMI = UseMI;
SReg = Reg;
}
Reg = Candidates.find_next(Reg);
}
- if (ScavengedReg != 0) {
- // First restore previously scavenged register.
- TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
- ScavengingFrameIndex, ScavengedRC);
- MachineBasicBlock::iterator II = prior(I);
- TRI->eliminateFrameIndex(II, SPAdj, this);
+ assert(ScavengedReg == 0 &&
+ "Scavenger slot is live, unable to scavenge another register!");
+
+ // Make sure SReg is marked as used. It could be considered available if it is
+ // one of the callee saved registers, but hasn't been spilled.
+ if (!isUsed(SReg)) {
+ MBB->addLiveIn(SReg);
+ setUsed(SReg);
}
+ // Spill the scavenged register before I.
TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
MachineBasicBlock::iterator II = prior(I);
TRI->eliminateFrameIndex(II, SPAdj, this);
+
+ // Restore the scavenged register before its use (or first terminator).
+ II = MaxUseMI
+ ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
+ TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
+ ScavengeRestore = prior(II);
ScavengedReg = SReg;
ScavengedRC = RC;
projects / oota-llvm.git / blobdiff