#define DEBUG_TYPE "reg-scavenging"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
-/// RedefinesSuperRegPart - Return true if the specified register is redefining
-/// part of a super-register.
-static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
- const TargetRegisterInfo *TRI) {
- bool SeenSuperUse = false;
- bool SeenSuperDef = false;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg())
- continue;
- if (TRI->isSuperRegister(SubReg, MO.getReg())) {
- if (MO.isUse())
- SeenSuperUse = true;
- else if (MO.isImplicit())
- SeenSuperDef = true;
- }
- }
-
- return SeenSuperDef && SeenSuperUse;
-}
-
-static bool RedefinesSuperRegPart(const MachineInstr *MI,
- const MachineOperand &MO,
- const TargetRegisterInfo *TRI) {
- assert(MO.isReg() && MO.isDef() && "Not a register def!");
- return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
-}
-
/// setUsed - Set the register and its sub-registers as being used.
-void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
+void RegScavenger::setUsed(unsigned Reg) {
RegsAvailable.reset(Reg);
- ImplicitDefed[Reg] = ImpDef;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs) {
+ unsigned SubReg = *SubRegs; ++SubRegs)
RegsAvailable.reset(SubReg);
- ImplicitDefed[SubReg] = ImpDef;
- }
}
/// setUnused - Set the register and its sub-registers as being unused.
void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
RegsAvailable.set(Reg);
- ImplicitDefed.reset(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
- if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
- RegsAvailable.set(SubReg);
- ImplicitDefed.reset(SubReg);
- }
+ RegsAvailable.set(SubReg);
+}
+
+bool RegScavenger::isAliasUsed(unsigned Reg) const {
+ if (isUsed(Reg))
+ return true;
+ for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R)
+ if (isUsed(*R))
+ return true;
+ return false;
+}
+
+void RegScavenger::initRegState() {
+ ScavengedReg = 0;
+ ScavengedRC = NULL;
+ ScavengeRestore = NULL;
+
+ // All registers started out unused.
+ RegsAvailable.set();
+
+ // Reserved registers are always used.
+ RegsAvailable ^= ReservedRegs;
+
+ // Live-in registers are in use.
+ if (!MBB || MBB->livein_empty())
+ return;
+ for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
+ E = MBB->livein_end(); I != E; ++I)
+ setUsed(*I);
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
"Target changed?");
+ // Self-initialize.
if (!MBB) {
NumPhysRegs = TRI->getNumRegs();
RegsAvailable.resize(NumPhysRegs);
- ImplicitDefed.resize(NumPhysRegs);
// Create reserved registers bitvector.
ReservedRegs = TRI->getReservedRegs(MF);
CalleeSavedRegs.set(CSRegs[i]);
}
- MBB = mbb;
- ScavengedReg = 0;
- ScavengedRC = NULL;
-
- // All registers started out unused.
- RegsAvailable.set();
-
- // Reserved registers are always used.
- RegsAvailable ^= ReservedRegs;
-
- // Live-in registers are in use.
- if (!MBB->livein_empty())
- for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
- E = MBB->livein_end(); I != E; ++I)
- setUsed(*I);
+ // RS used within emit{Pro,Epi}logue()
+ if (mbb != MBB) {
+ MBB = mbb;
+ initRegState();
+ }
Tracking = false;
}
void RegScavenger::restoreScavengedReg() {
- if (!ScavengedReg)
- return;
-
TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(MBBI);
ScavengedRC = NULL;
}
+#ifndef NDEBUG
/// isLiveInButUnusedBefore - Return true if register is livein the MBB not
/// not used before it reaches the MI that defines register.
static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
SmallPtrSet<MachineInstr*, 4> UsesInMBB;
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
UE = MRI->use_end(); UI != UE; ++UI) {
+ MachineOperand &UseMO = UI.getOperand();
+ if (UseMO.isReg() && UseMO.isUndef())
+ continue;
MachineInstr *UseMI = &*UI;
if (UseMI->getParent() == MBB)
UsesInMBB.insert(UseMI);
return false;
return true;
}
+#endif
+
+void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
+ BV.set(Reg);
+ for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
+ BV.set(*R);
+}
+
+void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) {
+ BV.set(Reg);
+ for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++)
+ BV.set(*R);
+}
void RegScavenger::forward() {
// Move ptr forward.
}
MachineInstr *MI = MBBI;
- const TargetInstrDesc &TID = MI->getDesc();
-
- // Reaching a terminator instruction. Restore a scavenged register (which
- // must be life out.
- if (TID.isTerminator())
- restoreScavengedReg();
- bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
+ if (MI == ScavengeRestore) {
+ ScavengedReg = 0;
+ ScavengedRC = NULL;
+ ScavengeRestore = NULL;
+ }
- // Separate register operands into 3 classes: uses, defs, earlyclobbers.
- SmallVector<const MachineOperand*, 4> UseMOs;
- SmallVector<const MachineOperand*, 4> DefMOs;
- SmallVector<const MachineOperand*, 4> EarlyClobberMOs;
+ // Find out which registers are early clobbered, killed, defined, and marked
+ // def-dead in this instruction.
+ BitVector EarlyClobberRegs(NumPhysRegs);
+ BitVector KillRegs(NumPhysRegs);
+ BitVector DefRegs(NumPhysRegs);
+ BitVector DeadRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || MO.getReg() == 0)
+ if (!MO.isReg() || MO.isUndef())
continue;
- if (MO.isUse())
- UseMOs.push_back(&MO);
- else if (MO.isEarlyClobber())
- EarlyClobberMOs.push_back(&MO);
- else
- DefMOs.push_back(&MO);
- }
-
- // Process uses first.
- BitVector UseRegs(NumPhysRegs);
- for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
- const MachineOperand &MO = *UseMOs[i];
- unsigned Reg = MO.getReg();
-
- if (!isUsed(Reg)) {
- // Register has been scavenged. Restore it!
- if (Reg == ScavengedReg)
- restoreScavengedReg();
- else
- assert(false && "Using an undefined register!");
- }
-
- if (MO.isKill() && !isReserved(Reg)) {
- UseRegs.set(Reg);
-
- // Mark sub-registers as used.
- for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs)
- UseRegs.set(SubReg);
- }
- }
-
- // Change states of all registers after all the uses are processed to guard
- // against multiple uses.
- setUnused(UseRegs);
-
- // Process early clobber defs then process defs. We can have a early clobber
- // that is dead, it should not conflict with a def that happens one "slot"
- // (see InstrSlots in LiveIntervalAnalysis.h) later.
- unsigned NumECs = EarlyClobberMOs.size();
- unsigned NumDefs = DefMOs.size();
-
- for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
- const MachineOperand &MO = (i < NumECs)
- ? *EarlyClobberMOs[i] : *DefMOs[i-NumECs];
unsigned Reg = MO.getReg();
-
- // If it's dead upon def, then it is now free.
- if (MO.isDead()) {
- setUnused(Reg, MI);
+ if (!Reg || isReserved(Reg))
continue;
- }
- // Skip two-address destination operand.
- if (TID.findTiedToSrcOperand(i) != -1) {
- assert(isUsed(Reg) && "Using an undefined register!");
- continue;
+ if (MO.isUse()) {
+ // Two-address operands implicitly kill.
+ if (MO.isKill() || MI->isRegTiedToDefOperand(i))
+ addRegWithSubRegs(KillRegs, Reg);
+ } else {
+ assert(MO.isDef());
+ if (MO.isDead())
+ addRegWithSubRegs(DeadRegs, Reg);
+ else
+ addRegWithSubRegs(DefRegs, Reg);
+ if (MO.isEarlyClobber())
+ addRegWithAliases(EarlyClobberRegs, Reg);
}
-
- // Skip is this is merely redefining part of a super-register.
- if (RedefinesSuperRegPart(MI, MO, TRI))
- continue;
-
- // Implicit def is allowed to "re-define" any register. Similarly,
- // implicitly defined registers can be clobbered.
- assert((isReserved(Reg) || isUnused(Reg) ||
- IsImpDef || isImplicitlyDefined(Reg) ||
- isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
- "Re-defining a live register!");
- setUsed(Reg, IsImpDef);
- }
-}
-
-void RegScavenger::backward() {
- assert(Tracking && "Not tracking states!");
- assert(MBBI != MBB->begin() && "Already at start of basic block!");
- // Move ptr backward.
- MBBI = prior(MBBI);
-
- MachineInstr *MI = MBBI;
- // Process defs first.
- const TargetInstrDesc &TID = MI->getDesc();
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isDef())
- continue;
- // Skip two-address destination operand.
- if (TID.findTiedToSrcOperand(i) != -1)
- continue;
- unsigned Reg = MO.getReg();
- assert(isUsed(Reg));
- if (!isReserved(Reg))
- setUnused(Reg, MI);
}
- // Process uses.
- BitVector UseRegs(NumPhysRegs);
+ // Verify uses and defs.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse())
+ if (!MO.isReg() || MO.isUndef())
continue;
unsigned Reg = MO.getReg();
- if (Reg == 0)
+ if (!Reg || isReserved(Reg))
continue;
- assert(isUnused(Reg) || isReserved(Reg));
- UseRegs.set(Reg);
-
- // Set the sub-registers as "used".
- for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs)
- UseRegs.set(SubReg);
+ if (MO.isUse()) {
+ assert(isUsed(Reg) && "Using an undefined register!");
+ assert(!EarlyClobberRegs.test(Reg) &&
+ "Using an early clobbered register!");
+ } else {
+ assert(MO.isDef());
+ assert((KillRegs.test(Reg) || isUnused(Reg) ||
+ isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
+ "Re-defining a live register!");
+ }
}
- setUsed(UseRegs);
+
+ // Commit the changes.
+ setUnused(KillRegs);
+ setUnused(DeadRegs);
+ setUsed(DefRegs);
}
void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
return (Reg == -1) ? 0 : Reg;
}
-/// calcDistanceToUse - Calculate the distance to the first use of the
-/// specified register.
-static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator I, unsigned Reg,
- const TargetRegisterInfo *TRI) {
- unsigned Dist = 0;
- I = next(I);
- while (I != MBB->end()) {
- Dist++;
- if (I->readsRegister(Reg, TRI))
- return Dist;
- I = next(I);
+/// DistanceMap - Keep track the distance of an MI from the current position.
+typedef DenseMap<MachineInstr*, unsigned> DistanceMap;
+
+/// Build a distance map for instructions from I to E.
+static void buildDistanceMap(DistanceMap &DM,
+ MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator E) {
+ DM.clear();
+ for (unsigned d = 0; I != E; ++I, ++d)
+ DM.insert(DistanceMap::value_type(I, d));
+}
+
+/// findFirstUse - Calculate the distance to the first use of the
+/// specified register in the range covered by DM.
+static MachineInstr *findFirstUse(const MachineBasicBlock *MBB,
+ const DistanceMap &DM,
+ unsigned Reg,
+ unsigned &Dist) {
+ const MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
+ MachineInstr *UseMI = 0;
+ Dist = ~0U;
+ for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
+ RE = MRI->reg_end(); RI != RE; ++RI) {
+ MachineInstr *UDMI = &*RI;
+ if (UDMI->getParent() != MBB)
+ continue;
+ DistanceMap::const_iterator DI = DM.find(UDMI);
+ if (DI == DM.end())
+ continue;
+ if (DI->second < Dist) {
+ Dist = DI->second;
+ UseMI = UDMI;
+ }
}
- return Dist + 1;
+ return UseMI;
}
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
// Mask off the registers which are not in the TargetRegisterClass.
BitVector Candidates(NumPhysRegs, false);
CreateRegClassMask(RC, Candidates);
- Candidates ^= ReservedRegs; // Do not include reserved registers.
+ // Do not include reserved registers.
+ Candidates ^= ReservedRegs & Candidates;
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
Candidates.reset(MO.getReg());
}
+ // Prepare to call findFirstUse() a number of times.
+ DistanceMap DM;
+ buildDistanceMap(DM, I, MBB->end());
+
// Find the register whose use is furthest away.
unsigned SReg = 0;
unsigned MaxDist = 0;
+ MachineInstr *MaxUseMI = 0;
int Reg = Candidates.find_first();
while (Reg != -1) {
- unsigned Dist = calcDistanceToUse(MBB, I, Reg, TRI);
+ unsigned Dist;
+ MachineInstr *UseMI = findFirstUse(MBB, DM, Reg, Dist);
+ for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
+ unsigned AsDist;
+ MachineInstr *AsUseMI = findFirstUse(MBB, DM, *AS, AsDist);
+ if (AsDist < Dist) {
+ Dist = AsDist;
+ UseMI = AsUseMI;
+ }
+ }
+
+ // If we found an unused register that is defined by a later instruction,
+ // there is no reason to spill it. We have probably found a callee-saved
+ // register that has been saved in the prologue, but happens to be unused at
+ // this point.
+ if (!isAliasUsed(Reg) && UseMI != NULL)
+ return Reg;
+
if (Dist >= MaxDist) {
MaxDist = Dist;
+ MaxUseMI = UseMI;
SReg = Reg;
}
Reg = Candidates.find_next(Reg);
}
- if (ScavengedReg != 0) {
- // First restore previously scavenged register.
- TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
- ScavengingFrameIndex, ScavengedRC);
- MachineBasicBlock::iterator II = prior(I);
- TRI->eliminateFrameIndex(II, SPAdj, this);
+ assert(ScavengedReg == 0 &&
+ "Scavenger slot is live, unable to scavenge another register!");
+
+ // Avoid infinite regress
+ ScavengedReg = SReg;
+
+ // Make sure SReg is marked as used. It could be considered available
+ // if it is one of the callee saved registers, but hasn't been spilled.
+ if (!isUsed(SReg)) {
+ MBB->addLiveIn(SReg);
+ setUsed(SReg);
}
+ // Spill the scavenged register before I.
TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
MachineBasicBlock::iterator II = prior(I);
TRI->eliminateFrameIndex(II, SPAdj, this);
- ScavengedReg = SReg;
+
+ // Restore the scavenged register before its use (or first terminator).
+ II = MaxUseMI
+ ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
+ TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
+ ScavengeRestore = prior(II);
+ // Doing this here leads to infinite regress.
+ // ScavengedReg = SReg;
ScavengedRC = RC;
return SReg;
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