add trivial support for passing label definitions through the MCStreamer.

[oota-llvm.git] / lib / CodeGen / ScheduleDAG.cpp

diff --git a/lib/CodeGen/ScheduleDAG.cpp b/lib/CodeGen/ScheduleDAG.cpp
index 730080d0fa4e36e49f9c476853d148686795aee3..a8452dff272b8d741898d56d76efcb4c8b9d9c0f 100644 (file)
--- a/lib/CodeGen/ScheduleDAG.cpp
+++ b/lib/CodeGen/ScheduleDAG.cpp
@@ -14,6 +14,7 @@
 
 #define DEBUG_TYPE "pre-RA-sched"
 #include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
@@ -21,14 +22,14 @@
 #include <climits>
 using namespace llvm;
 
-ScheduleDAG::ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
-                         const TargetMachine &tm)
-  : DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) {
-  TII = TM.getInstrInfo();
-  MF  = BB->getParent();
-  TRI = TM.getRegisterInfo();
-  TLI = TM.getTargetLowering();
-  ConstPool = MF->getConstantPool();
+ScheduleDAG::ScheduleDAG(MachineFunction &mf)
+  : TM(mf.getTarget()),
+    TII(TM.getInstrInfo()),
+    TRI(TM.getRegisterInfo()),
+    TLI(TM.getTargetLowering()),
+    MF(mf), MRI(mf.getRegInfo()),
+    ConstPool(MF.getConstantPool()),
+    EntrySU(), ExitSU() {
 }
 
 ScheduleDAG::~ScheduleDAG() {}
@@ -46,9 +47,18 @@ void ScheduleDAG::dumpSchedule() const {
 
 /// Run - perform scheduling.
 ///
-void ScheduleDAG::Run() {
+void ScheduleDAG::Run(MachineBasicBlock *bb,
+                      MachineBasicBlock::iterator insertPos) {
+  BB = bb;
+  InsertPos = insertPos;
+
+  SUnits.clear();
+  Sequence.clear();
+  EntrySU = SUnit();
+  ExitSU = SUnit();
+
   Schedule();
-  
+
   DOUT << "*** Final schedule ***\n";
   DEBUG(dumpSchedule());
   DOUT << "\n";
@@ -59,8 +69,9 @@ void ScheduleDAG::Run() {
 /// specified node.
 void SUnit::addPred(const SDep &D) {
   // If this node already has this depenence, don't add a redundant one.
-  for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
-    if (Preds[i] == D)
+  for (SmallVector<SDep, 4>::const_iterator I = Preds.begin(), E = Preds.end();
+       I != E; ++I)
+    if (*I == D)
       return;
   // Now add a corresponding succ to N.
   SDep P = D;
@@ -75,8 +86,8 @@ void SUnit::addPred(const SDep &D) {
     ++NumPredsLeft;
   if (!isScheduled)
     ++N->NumSuccsLeft;
-  N->Succs.push_back(P);
   Preds.push_back(D);
+  N->Succs.push_back(P);
   if (P.getLatency() != 0) {
     this->setDepthDirty();
     N->setHeightDirty();
@@ -105,8 +116,8 @@ void SUnit::removePred(const SDep &D) {
         }
       assert(FoundSucc && "Mismatching preds / succs lists!");
       Preds.erase(I);
-      // Update the bookkeeping;
-      if (D.getKind() == SDep::Data) {
+      // Update the bookkeeping.
+      if (P.getKind() == SDep::Data) {
         --NumPreds;
         --N->NumSuccs;
       }
@@ -557,3 +568,5 @@ void ScheduleDAGTopologicalSort::Allocate(int n, int index) {
 ScheduleDAGTopologicalSort::ScheduleDAGTopologicalSort(
                                                      std::vector<SUnit> &sunits)
  : SUnits(sunits) {}
+
+ScheduleHazardRecognizer::~ScheduleHazardRecognizer() {}