This is to fix the bug in IntrinsicLowering.cpp,
[oota-llvm.git] / lib / CodeGen / ScheduleDAGEmit.cpp
index ce3283dc3df1adda09f7c74886fa44db3c99217d..0c8435da6cbdf6f98aef026d30ca0f0d51e54785 100644 (file)
 using namespace llvm;
 
 void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
-  MI->addMemOperand(*MF, MO);
+  MI->addMemOperand(MF, MO);
 }
 
 void ScheduleDAG::EmitNoop() {
-  TII->insertNoop(*BB, BB->end());
+  TII->insertNoop(*BB, End);
 }
 
-void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
+void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
                                   DenseMap<SUnit*, unsigned> &VRBaseMap) {
   for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
        I != E; ++I) {
-    if (I->isCtrl) continue;  // ignore chain preds
-    if (I->Dep->CopyDstRC) {
+    if (I->isCtrl()) continue;  // ignore chain preds
+    if (I->getSUnit()->CopyDstRC) {
       // Copy to physical register.
-      DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->Dep);
+      DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
       assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
       // Find the destination physical register.
       unsigned Reg = 0;
       for (SUnit::const_succ_iterator II = SU->Succs.begin(),
              EE = SU->Succs.end(); II != EE; ++II) {
-        if (I->Reg) {
-          Reg = I->Reg;
+        if (II->getReg()) {
+          Reg = II->getReg();
           break;
         }
       }
-      assert(I->Reg && "Unknown physical register!");
-      TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
+      TII->copyRegToReg(*BB, End, Reg, VRI->second,
                         SU->CopyDstRC, SU->CopySrcRC);
     } else {
       // Copy from physical register.
-      assert(I->Reg && "Unknown physical register!");
+      assert(I->getReg() && "Unknown physical register!");
       unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
       bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
       isNew = isNew; // Silence compiler warning.
       assert(isNew && "Node emitted out of order - early");
-      TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
+      TII->copyRegToReg(*BB, End, VRBase, I->getReg(),
                         SU->CopyDstRC, SU->CopySrcRC);
     }
     break;