// otherwise - N should be replaced by the returned Operand.
//
SDOperand visitTokenFactor(SDNode *N);
+ SDOperand visitMERGE_VALUES(SDNode *N);
SDOperand visitADD(SDNode *N);
SDOperand visitSUB(SDNode *N);
SDOperand visitADDC(SDNode *N);
switch(N->getOpcode()) {
default: break;
case ISD::TokenFactor: return visitTokenFactor(N);
+ case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
case ISD::ADD: return visitADD(N);
case ISD::SUB: return visitSUB(N);
case ISD::ADDC: return visitADDC(N);
return Result;
}
+/// MERGE_VALUES can always be eliminated.
+SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) {
+ WorkListRemover DeadNodes(*this);
+ for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+ DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i),
+ &DeadNodes);
+ removeFromWorkList(N);
+ DAG.DeleteNode(N);
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+}
+
+
static
SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
MVT::ValueType VT = N0.getValueType();
Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
}
- MVT::ValueType VT = MVT::getVectorType(DstEltVT,
- Ops.size());
+ MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
// Finally, this must be the case where we are shrinking elements: each input
// turns into multiple outputs.
+ bool isS2V = ISD::isScalarToVector(BV);
unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
+ MVT::ValueType VT = MVT::getVectorType(DstEltVT,
+ NumOutputsPerInput * BV->getNumOperands());
SmallVector<SDOperand, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
continue;
}
uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
-
for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
- OpVal >>= DstBitSize;
Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
+ if (isS2V && i == 0 && j == 0 && ThisVal == OpVal)
+ // Simply turn this into a SCALAR_TO_VECTOR of the new type.
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]);
+ OpVal >>= DstBitSize;
}
// For big endian targets, swap the order of the pieces of each element.
if (TLI.isBigEndian())
std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
}
- MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}