Refactor a bunch of includes so that TargetMachine.h doesn't have to include

[oota-llvm.git] / lib / CodeGen / SelectionDAG / DAGCombiner.cpp

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9c469b53c71f22b5db66b6620a1c77e81eccd110..0aaee2f04320ae1115cfd74ef64c3f54f80ccfa8 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -76,7 +76,7 @@ namespace {
     SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
       ++NodesCombined;
       DEBUG(std::cerr << "\nReplacing "; N->dump();
-            std::cerr << "\nWith: "; To[0].Val->dump();
+            std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
             std::cerr << " and " << To.size()-1 << " other values\n");
       std::vector<SDNode*> NowDead;
       DAG.ReplaceAllUsesWith(N, To, &NowDead);
@@ -128,7 +128,7 @@ namespace {
       // Replace the old value with the new one.
       ++NodesCombined;
       DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
-            std::cerr << "\nWith: "; TLO.New.Val->dump());
+            std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG));
 
       std::vector<SDNode*> NowDead;
       DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
@@ -577,7 +577,7 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
       // mechanics for us, we have no work to do in this case.
       if (RV.Val != N) {
         DEBUG(std::cerr << "\nReplacing "; N->dump();
-              std::cerr << "\nWith: "; RV.Val->dump();
+              std::cerr << "\nWith: "; RV.Val->dump(&DAG);
               std::cerr << '\n');
         std::vector<SDNode*> NowDead;
         DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
@@ -680,7 +680,8 @@ SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
   // If the token factor has two operands and one is the entry token, replace
   // the token factor with the other operand.
   if (N->getNumOperands() == 2) {
-    if (N->getOperand(0).getOpcode() == ISD::EntryToken)
+    if (N->getOperand(0).getOpcode() == ISD::EntryToken ||
+        N->getOperand(0) == N->getOperand(1))
       return N->getOperand(1);
     if (N->getOperand(1).getOpcode() == ISD::EntryToken)
       return N->getOperand(0);
@@ -694,8 +695,11 @@ SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
       Changed = true;
       for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
         Ops.push_back(Op.getOperand(j));
-    } else {
+    } else if (i == 0 || N->getOperand(i) != N->getOperand(i-1)) {
       Ops.push_back(Op);
+    } else {
+      // Deleted an operand that was the same as the last one.
+      Changed = true;
     }
   }
   if (Changed)
@@ -1575,6 +1579,11 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
     }
   }
   
+  // Simplify, based on bits shifted out of the LHS. 
+  if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
+    return SDOperand(N, 0);
+  
+  
   // If the sign bit is known to be zero, switch this to a SRL.
   if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
     return DAG.getNode(ISD::SRL, VT, N0, N1);
@@ -1931,7 +1940,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   unsigned EVTBits = MVT::getSizeInBits(EVT);
   
   // fold (sext_in_reg c1) -> c1
-  if (isa<ConstantSDNode>(N0))
+  if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
     return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
   
   // If the input is already sign extended, just drop the extension.
@@ -1943,10 +1952,25 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
       EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
     return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
   }
-  
+
   // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
   if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
     return DAG.getZeroExtendInReg(N0, EVT);
+  
+  // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
+  // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
+  // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
+  if (N0.getOpcode() == ISD::SRL) {
+    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
+      if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
+        // We can turn this into an SRA iff the input to the SRL is already sign
+        // extended enough.
+        unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
+        if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
+          return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
+      }
+  }
+  
   // fold (sext_inreg (extload x)) -> (sextload x)
   if (N0.getOpcode() == ISD::EXTLOAD && 
       EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&