LegalizedNodes.insert(std::make_pair(To, To));
}
void AddPromotedOperand(SDOperand From, SDOperand To) {
- bool isNew = PromotedNodes.insert(std::make_pair(From, To));
+ bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
assert(isNew && "Got into the map somehow?");
// If someone requests legalization of the new node, return itself.
LegalizedNodes.insert(std::make_pair(To, To));
}
public:
-
- SelectionDAGLegalize(SelectionDAG &DAG);
+ explicit SelectionDAGLegalize(SelectionDAG &DAG);
/// getTypeAction - Return how we should legalize values of this type, either
/// it is already legal or we need to expand it into multiple registers of
SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
- } else if (SizeDiff < 0)
- SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
+ } else if (SizeDiff < 0) {
+ SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
+ SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
+ DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
+ }
// Clear the sign bit of first operand.
SDOperand Mask2 = (VT == MVT::f64)
Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
SDOperand Ops[] = { Result, Chain };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
- Ops, 2);
+ return DAG.getMergeValues(Ops, 2);
}
assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
"Unaligned load of unsupported type.");
Hi.getValue(1));
SDOperand Ops[] = { Result, TF };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
+ return DAG.getMergeValues(Ops, 2);
}
/// UnrollVectorOp - We know that the given vector has a legal type, however
MVT PtrVT = TLI.getPointerTy();
SDOperand StackPtr = DAG.CreateStackTemporary(VT);
- FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
- int SPFI = StackPtrFI->getIndex();
+ int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
// Store the vector.
SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
- PseudoSourceValue::getFixedStack(),
- SPFI);
+ PseudoSourceValue::getFixedStack(SPFI), 0);
// Truncate or zero extend offset to target pointer type.
unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
// Store the scalar value.
Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
- PseudoSourceValue::getFixedStack(), SPFI, EltVT);
+ PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
// Load the updated vector.
- return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI);
+ return DAG.getLoad(VT, Ch, StackPtr,
+ PseudoSourceValue::getFixedStack(SPFI), 0);
}
/// LegalizeOp - We know that the specified value has a legal type, and
case ISD::VALUETYPE:
case ISD::SRCVALUE:
case ISD::MEMOPERAND:
- case ISD::STRING:
case ISD::CONDCODE:
case ISD::ARG_FLAGS:
// Primitives must all be legal.
// Fall Thru
case TargetLowering::Legal: {
SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
- Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
- Ops, 2);
+ Result = DAG.getMergeValues(Ops, 2);
break;
}
}
// Fall Thru
case TargetLowering::Legal: {
SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
- Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
- Ops, 2);
+ Result = DAG.getMergeValues(Ops, 2);
break;
}
}
return Result.getValue(Op.ResNo);
}
- case ISD::LOCATION:
- assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
+ case ISD::DBG_STOPPOINT:
+ assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
- switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
+ switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
case TargetLowering::Promote:
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
- bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
+ bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
+ const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
if (MMI && (useDEBUG_LOC || useLABEL)) {
- const std::string &FName =
- cast<StringSDNode>(Node->getOperand(3))->getValue();
- const std::string &DirName =
- cast<StringSDNode>(Node->getOperand(4))->getValue();
- unsigned SrcFile = MMI->RecordSource(DirName, FName);
-
- SmallVector<SDOperand, 8> Ops;
- Ops.push_back(Tmp1); // chain
- SDOperand LineOp = Node->getOperand(1);
- SDOperand ColOp = Node->getOperand(2);
+ const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
+ unsigned SrcFile = MMI->RecordSource(CompileUnit);
+
+ unsigned Line = DSP->getLine();
+ unsigned Col = DSP->getColumn();
if (useDEBUG_LOC) {
- Ops.push_back(LineOp); // line #
- Ops.push_back(ColOp); // col #
- Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
- Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
+ SDOperand Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
+ DAG.getConstant(Col, MVT::i32),
+ DAG.getConstant(SrcFile, MVT::i32) };
+ Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
} else {
- unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
- unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
- Ops.push_back(DAG.getConstant(ID, MVT::i32));
- Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
- Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
+ Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
}
} else {
Result = Tmp1; // chain
}
break;
}
- case TargetLowering::Legal:
- if (Tmp1 != Node->getOperand(0) ||
- getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
- SmallVector<SDOperand, 8> Ops;
- Ops.push_back(Tmp1);
- if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
- Ops.push_back(Node->getOperand(1)); // line # must be legal.
- Ops.push_back(Node->getOperand(2)); // col # must be legal.
- } else {
- // Otherwise promote them.
- Ops.push_back(PromoteOp(Node->getOperand(1)));
- Ops.push_back(PromoteOp(Node->getOperand(2)));
- }
- Ops.push_back(Node->getOperand(3)); // filename must be legal.
- Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
- Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
+ case TargetLowering::Legal: {
+ LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
+ if (Action == Legal && Tmp1 == Node->getOperand(0))
+ break;
+
+ SmallVector<SDOperand, 8> Ops;
+ Ops.push_back(Tmp1);
+ if (Action == Legal) {
+ Ops.push_back(Node->getOperand(1)); // line # must be legal.
+ Ops.push_back(Node->getOperand(2)); // col # must be legal.
+ } else {
+ // Otherwise promote them.
+ Ops.push_back(PromoteOp(Node->getOperand(1)));
+ Ops.push_back(PromoteOp(Node->getOperand(2)));
}
+ Ops.push_back(Node->getOperand(3)); // filename must be legal.
+ Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
+ Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
break;
}
+ }
break;
case ISD::DECLARE:
assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
- case TargetLowering::Legal:
+ case TargetLowering::Legal: {
+ LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
- Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
- Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
- Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
+ if (Action == Legal && Tmp1 == Node->getOperand(0))
+ break;
+ if (Action == Legal) {
+ Tmp2 = Node->getOperand(1);
+ Tmp3 = Node->getOperand(2);
+ Tmp4 = Node->getOperand(3);
+ } else {
+ Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
+ Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
+ Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
+ }
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
break;
}
+ }
break;
- case ISD::LABEL:
- assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
- switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
+ case ISD::DBG_LABEL:
+ case ISD::EH_LABEL:
+ assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
+ switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
- Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
- Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+ Result = DAG.UpdateNodeOperands(Result, Tmp1);
break;
case TargetLowering::Expand:
Result = LegalizeOp(Node->getOperand(0));
AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
- }
+ }
case ISD::ATOMIC_LOAD_ADD:
case ISD::ATOMIC_LOAD_SUB:
case ISD::ATOMIC_LOAD_AND:
for (unsigned int x = 0; x < num_operands; ++x)
Ops[x] = LegalizeOp(Node->getOperand(x));
Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
-
+
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Custom:
Result = TLI.LowerOperation(Result, DAG);
break;
case TargetLowering::Expand:
- Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0);
+ Result = SDOperand(TLI.ReplaceNodeResults(Op.Val, DAG),0);
break;
case TargetLowering::Legal:
break;
AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
- }
+ }
case ISD::Constant: {
ConstantSDNode *CN = cast<ConstantSDNode>(Node);
unsigned opAction =
LC = RTLIB::FPTOSINT_F32_I32;
else if (OVT == MVT::f64)
LC = RTLIB::FPTOSINT_F64_I32;
+ else if (OVT == MVT::f80)
+ LC = RTLIB::FPTOSINT_F80_I32;
+ else if (OVT == MVT::ppcf128)
+ LC = RTLIB::FPTOSINT_PPCF128_I32;
else
assert(0 && "Unexpected i32-to-fp conversion!");
} else if (VT == MVT::i64) {
Tmp2 = Node->getOperand(1); // Get the pointer.
if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
- Result = TLI.CustomPromoteOperation(Tmp3, DAG);
+ Result = TLI.LowerOperation(Tmp3, DAG);
} else {
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
MVT VT = LHS.getValueType();
if (VT == MVT::f32 || VT == MVT::f64) {
// Expand into one or more soft-fp libcall(s).
- RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
+ RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
switch (cast<CondCodeSDNode>(CC)->get()) {
case ISD::SETEQ:
case ISD::SETOEQ:
default: assert(0 && "Unsupported FP setcc!");
}
}
-
+
SDOperand Dummy;
- Tmp1 = ExpandLibCall(LC1,
- DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
+ SDOperand Ops[2] = { LHS, RHS };
+ Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getConstant(0, MVT::i32);
CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
CC);
- LHS = ExpandLibCall(LC2,
- DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
+ LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp2 = SDOperand();
}
- LHS = Tmp1;
+ LHS = LegalizeOp(Tmp1);
RHS = Tmp2;
return;
}
MVT SlotVT,
MVT DestVT) {
// Create the stack frame object.
- SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
-
+ unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
+ SrcOp.getValueType().getTypeForMVT());
+ SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
+
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
int SPFI = StackPtrFI->getIndex();
-
+
unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
unsigned SlotSize = SlotVT.getSizeInBits();
unsigned DestSize = DestVT.getSizeInBits();
+ unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
+ DestVT.getTypeForMVT());
// Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT.
SDOperand Store;
+
if (SrcSize > SlotSize)
Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
- PseudoSourceValue::getFixedStack(),
- SPFI, SlotVT);
+ PseudoSourceValue::getFixedStack(SPFI), 0,
+ SlotVT, false, SrcAlign);
else {
assert(SrcSize == SlotSize && "Invalid store");
Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
- PseudoSourceValue::getFixedStack(),
- SPFI);
+ PseudoSourceValue::getFixedStack(SPFI), 0,
+ false, SrcAlign);
}
// Result is a load from the stack slot.
if (SlotSize == DestSize)
- return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
+ return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
assert(SlotSize < DestSize && "Unknown extension!");
- return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
+ return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
+ false, DestAlign);
}
SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
int SPFI = StackPtrFI->getIndex();
SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
- PseudoSourceValue::getFixedStack(), SPFI);
+ PseudoSourceValue::getFixedStack(SPFI), 0);
return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
- PseudoSourceValue::getFixedStack(), SPFI);
+ PseudoSourceValue::getFixedStack(SPFI), 0);
}
// Okay, we found the operation and type to use.
SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
-
+
// If the operation produces an invalid type, it must be custom lowered. Use
// the target lowering hooks to expand it. Just keep the low part of the
// expanded operation, we know that we're truncating anyway.
if (getTypeAction(NewOutTy) == Expand) {
- Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
+ Operation = SDOperand(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
assert(Operation.Val && "Didn't return anything");
}
-
+
// Truncate the result of the extended FP_TO_*INT operation to the desired
// size.
return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
}
// Remember in a map if the values will be reused later.
- bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
+ bool isNew =
+ ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
assert(isNew && "Value already expanded?!?");
}
}
break;
}
+ case ISD::SELECT_CC: {
+ SDOperand CondLHS = Node->getOperand(0);
+ SDOperand CondRHS = Node->getOperand(1);
+ SDOperand CondCode = Node->getOperand(4);
+
+ SDOperand LL, LH, RL, RH;
+ SplitVectorOp(Node->getOperand(2), LL, LH);
+ SplitVectorOp(Node->getOperand(3), RL, RH);
+
+ // Handle a simple select with vector operands.
+ Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
+ LL, RL, CondCode);
+ Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
+ LH, RH, CondCode);
+ break;
+ }
case ISD::VSETCC: {
SDOperand LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(0), LL, LH);
// The input is a scalar or single-element vector.
// Lower to a store/load so that it can be split.
// FIXME: this could be improved probably.
- SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
- FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
+ unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
+ Op.getValueType().getTypeForMVT());
+ SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
+ int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
SDOperand St = DAG.getStore(DAG.getEntryNode(),
InOp, Ptr,
- PseudoSourceValue::getFixedStack(),
- FI->getIndex());
+ PseudoSourceValue::getFixedStack(FI), 0);
InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
- PseudoSourceValue::getFixedStack(),
- FI->getIndex());
+ PseudoSourceValue::getFixedStack(FI), 0);
}
// Split the vector and convert each of the pieces now.
SplitVectorOp(InOp, Lo, Hi);
ScalarizeVectorOp(Op.getOperand(1)),
ScalarizeVectorOp(Op.getOperand(2)));
break;
+ case ISD::SELECT_CC:
+ Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
+ Node->getOperand(1),
+ ScalarizeVectorOp(Op.getOperand(2)),
+ ScalarizeVectorOp(Op.getOperand(3)),
+ Node->getOperand(4));
+ break;
case ISD::VSETCC: {
SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0));
SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1));
projects / oota-llvm.git / blobdiff