Formatting - no functional change.

[oota-llvm.git] / lib / CodeGen / SelectionDAG / LegalizeIntegerTypes.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 7fea9c8a8c35d7e546d05a7c72ee73ca7f5a7310..9e4ff4a8a01c3999da7a9fae51c02f66013bb060 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -272,8 +272,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
   if (TLI.isBigEndian())
     std::swap(Lo, Hi);
 
-  SDValue Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
-                              DAG.getConstant(1, TLI.getShiftAmountTy()));
+  SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx);
   return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
 }
 
@@ -365,10 +364,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
-  assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
-         && "SetCC type is not legal??");
-  return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
-                     N->getOperand(0), N->getOperand(1), N->getOperand(2));
+  MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+  MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
+  assert(isTypeLegal(SVT) && "SetCC type not legal??");
+  assert(NVT.getSizeInBits() <= SVT.getSizeInBits() &&
+         "Integer type overpromoted?");
+  return DAG.getNode(ISD::TRUNCATE, NVT,
+                     DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
+                                 N->getOperand(1), N->getOperand(2)));
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
@@ -1195,7 +1198,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
   MVT NVT = Lo.getValueType();
 
   SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
-                                     DAG.getConstant(0, NVT), ISD::SETNE);
+                                   DAG.getConstant(0, NVT), ISD::SETNE);
 
   SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
   SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
@@ -1223,7 +1226,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
   MVT NVT = Lo.getValueType();
 
   SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
-                                     DAG.getConstant(0, NVT), ISD::SETNE);
+                                   DAG.getConstant(0, NVT), ISD::SETNE);
 
   SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
   SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
@@ -2029,8 +2032,8 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
     SDValue Lo, Hi;
     GetExpandedInteger(Op, Lo, Hi);
     SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
-                                     DAG.getConstant(0, Hi.getValueType()),
-                                     ISD::SETLT);
+                                   DAG.getConstant(0, Hi.getValueType()),
+                                   ISD::SETLT);
 
     // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
     SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
@@ -2041,13 +2044,17 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
     SDValue Four = DAG.getIntPtrConstant(4);
     if (TLI.isBigEndian()) std::swap(Zero, Four);
     SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
-                                   Zero, Four);
+                                 Zero, Four);
+    unsigned Alignment =
+      1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
     FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
+    Alignment = std::min(Alignment, 4u);
 
     // Load the value out, extending it from f32 to the destination float type.
     // FIXME: Avoid the extend by constructing the right constant pool?
     SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
-                                     FudgePtr, NULL, 0, MVT::f32);
+                                   FudgePtr, NULL, 0, MVT::f32,
+                                   false, Alignment);
     return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
   }