case Legal:
break;
case PromoteInteger:
- if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
+ if (OutVT.bitsEq(NInVT))
// The input promotes to the same size. Convert the promoted value.
return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
break;
// Hi if it was odd.
SDValue Lo = Elt;
SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
- DAG.getConstant(OldVT.getSizeInBits(),
- TLI.getShiftAmountTy()));
+ DAG.getConstant(OldVT.getSizeInBits(),
+ TLI.getShiftAmountTy()));
if (TLI.isBigEndian())
std::swap(Lo, Hi);
if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
SDValue Res = GetPromotedInteger(N->getOperand(0));
- assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
- "Extension doesn't make sense!");
+ assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
// If the result and operand types are the same after promotion, simplify
// to an in-register extension.
// Convert to the expected type.
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- assert(NVT.getSizeInBits() <= SVT.getSizeInBits() &&
- "Integer type overpromoted?");
+ assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
return DAG.getNode(ISD::TRUNCATE, NVT, SetCC);
}
}
SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
+ MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Res;
switch (getTypeAction(N->getOperand(0).getValueType())) {
break;
}
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
- "Truncation doesn't make sense!");
- if (Res.getValueType() == NVT)
- return Res;
-
// Truncate to NVT instead of VT
return DAG.getNode(ISD::TRUNCATE, NVT, Res);
}
NewLHS = GetPromotedInteger(NewLHS);
NewRHS = GetPromotedInteger(NewRHS);
- // Otherwise, we have to insert explicit sign or zero extends. Note
- // that we could insert sign extends for ALL conditions, but zero extend
- // is cheaper on many machines (an AND instead of two shifts), so prefer
- // it.
+ // We have to insert explicit sign or zero extends. Note that we could
+ // insert sign extends for ALL conditions, but zero extend is cheaper on
+ // many machines (an AND instead of two shifts), so prefer it.
switch (CCCode) {
default: assert(0 && "Unknown integer comparison!");
case ISD::SETEQ:
// around the problem.
MVT SVT = TLI.getSetCCResultType(N->getOperand(1));
assert(isTypeLegal(SVT) && "Illegal SetCC type!");
- assert(Cond.getValueSizeInBits() <= SVT.getSizeInBits() &&
- "Unexpected SetCC type!");
+ assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
// Make sure the extra bits conform to getSetCCResultContents. There are
// two sets of extra bits: those in Cond, which come from type promotion,