//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "sched"
+#define DEBUG_TYPE "pre-RA-sched"
+#include "llvm/Type.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
-#include <iostream>
using namespace llvm;
-
/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
/// This SUnit graph is similar to the SelectionDAG, but represents flagged
/// together nodes with a single SUnit.
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
for (unsigned i = 0, ee = TII->getNumOperands(Opc); i != ee; ++i) {
- if (TII->getOperandConstraint(Opc, i,
- TargetInstrInfo::TIED_TO) != -1) {
+ if (TII->getOperandConstraint(Opc, i, TOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
break;
}
return;
}
-static void CalculateDepths(SUnit &SU, unsigned Depth) {
- if (SU.Depth == 0 || Depth > SU.Depth) {
- SU.Depth = Depth;
- for (SUnit::succ_iterator I = SU.Succs.begin(), E = SU.Succs.end();
- I != E; ++I)
- CalculateDepths(*I->first, Depth+1);
- }
-}
-
void ScheduleDAG::CalculateDepths() {
- SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
- ::CalculateDepths(*Entry, 0U);
+ std::vector<std::pair<SUnit*, unsigned> > WorkList;
for (unsigned i = 0, e = SUnits.size(); i != e; ++i)
- if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
- ::CalculateDepths(SUnits[i], 0U);
+ if (SUnits[i].Preds.size() == 0/* && &SUnits[i] != Entry*/)
+ WorkList.push_back(std::make_pair(&SUnits[i], 0U));
+
+ while (!WorkList.empty()) {
+ SUnit *SU = WorkList.back().first;
+ unsigned Depth = WorkList.back().second;
+ WorkList.pop_back();
+ if (SU->Depth == 0 || Depth > SU->Depth) {
+ SU->Depth = Depth;
+ for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
+ I != E; ++I)
+ WorkList.push_back(std::make_pair(I->first, Depth+1));
}
-}
-
-static void CalculateHeights(SUnit &SU, unsigned Height) {
- if (SU.Height == 0 || Height > SU.Height) {
- SU.Height = Height;
- for (SUnit::pred_iterator I = SU.Preds.begin(), E = SU.Preds.end();
- I != E; ++I)
- CalculateHeights(*I->first, Height+1);
}
}
+
void ScheduleDAG::CalculateHeights() {
+ std::vector<std::pair<SUnit*, unsigned> > WorkList;
SUnit *Root = SUnitMap[DAG.getRoot().Val];
- ::CalculateHeights(*Root, 0U);
+ WorkList.push_back(std::make_pair(Root, 0U));
+
+ while (!WorkList.empty()) {
+ SUnit *SU = WorkList.back().first;
+ unsigned Height = WorkList.back().second;
+ WorkList.pop_back();
+ if (SU->Height == 0 || Height > SU->Height) {
+ SU->Height = Height;
+ for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
+ I != E; ++I)
+ WorkList.push_back(std::make_pair(I->first, Height+1));
+ }
+ }
}
/// CountResults - The results of target nodes have register or immediate
? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
}
-static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
- MachineInstr *MI,
- unsigned NumResults,
- SSARegMap *RegMap,
- const TargetInstrInfo *TII,
- const TargetInstrDescriptor &II) {
- // Create the result registers for this node and add the result regs to
- // the machine instruction.
- unsigned ResultReg =
- RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
- MI->addRegOperand(ResultReg, true);
- for (unsigned i = 1; i != NumResults; ++i) {
- const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
- assert(RC && "Isn't a register operand!");
- MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
+static void CreateVirtualRegisters(SDNode *Node,
+ unsigned NumResults,
+ const MRegisterInfo *MRI,
+ MachineInstr *MI,
+ SSARegMap *RegMap,
+ const TargetInstrInfo *TII,
+ const TargetInstrDescriptor &II,
+ DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ for (unsigned i = 0; i < NumResults; ++i) {
+ // If the specific node value is only used by a CopyToReg and the dest reg
+ // is a vreg, use the CopyToReg'd destination register instead of creating
+ // a new vreg.
+ unsigned VRBase = 0;
+ for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
+ UI != E; ++UI) {
+ SDNode *Use = *UI;
+ if (Use->getOpcode() == ISD::CopyToReg &&
+ Use->getOperand(2).Val == Node &&
+ Use->getOperand(2).ResNo == i) {
+ unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
+ if (MRegisterInfo::isVirtualRegister(Reg)) {
+ VRBase = Reg;
+ MI->addRegOperand(Reg, true);
+ break;
+ }
+ }
+ }
+
+ if (VRBase == 0) {
+ // Create the result registers for this node and add the result regs to
+ // the machine instruction.
+ const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
+ assert(RC && "Isn't a register operand!");
+ VRBase = RegMap->createVirtualRegister(RC);
+ MI->addRegOperand(VRBase, true);
+ }
+
+ bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
+ assert(isNew && "Node emitted out of order - early");
}
- return ResultReg;
}
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
-static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) {
- std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
+static unsigned getVR(SDOperand Op, DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDOperand, unsigned>::iterator I = VRBaseMap.find(Op);
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
- return I->second + Op.ResNo;
+ return I->second;
}
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
const TargetInstrDescriptor *II,
- std::map<SDNode*, unsigned> &VRBaseMap) {
+ DenseMap<SDOperand, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, false);
+ const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ bool isOptDef = (IIOpNum < TID->numOperands)
+ ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
+ MI->addRegOperand(VReg, isOptDef);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
const TargetRegisterClass *RC =
getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == RC &&
- "Register class of operand and regclass of use don't agree!");
+ const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
+ if (VRC != RC) {
+ cerr << "Register class of operand and regclass of use don't agree!\n";
+#ifndef NDEBUG
+ cerr << "Operand = " << IIOpNum << "\n";
+ cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
+ cerr << "MI = "; MI->print(cerr);
+ cerr << "VReg = " << VReg << "\n";
+ cerr << "VReg RegClass size = " << VRC->getSize()
+ << ", align = " << VRC->getAlignment() << "\n";
+ cerr << "Expected RegClass size = " << RC->getSize()
+ << ", align = " << RC->getAlignment() << "\n";
+#endif
+ cerr << "Fatal error, aborting.\n";
+ abort();
+ }
}
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op)) {
MI->addImmOperand(C->getValue());
- } else if (RegisterSDNode*R =
+ } else if (RegisterSDNode *R =
dyn_cast<RegisterSDNode>(Op)) {
MI->addRegOperand(R->getReg(), false);
} else if (GlobalAddressSDNode *TGA =
const Type *Type = CP->getType();
// MachineConstantPool wants an explicit alignment.
if (Align == 0) {
- if (Type == Type::DoubleTy)
- Align = 3; // always 8-byte align doubles.
- else {
- Align = TM.getTargetData()->getTypeAlignmentShift(Type);
- if (Align == 0) {
- // Alignment of packed types. FIXME!
- Align = TM.getTargetData()->getTypeSize(Type);
- Align = Log2_64(Align);
- }
+ Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
+ if (Align == 0) {
+ // Alignment of vector types. FIXME!
+ Align = TM.getTargetData()->getTypeSize(Type);
+ Align = Log2_64(Align);
}
}
}
+// Returns the Register Class of a physical register
+static const TargetRegisterClass *getPhysicalRegisterRegClass(
+ const MRegisterInfo *MRI,
+ MVT::ValueType VT,
+ unsigned reg) {
+ assert(MRegisterInfo::isPhysicalRegister(reg) &&
+ "reg must be a physical register");
+ // Pick the register class of the right type that contains this physreg.
+ for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
+ E = MRI->regclass_end(); I != E; ++I)
+ if ((*I)->hasType(VT) && (*I)->contains(reg))
+ return *I;
+ assert(false && "Couldn't find the register class");
+ return 0;
+}
/// EmitNode - Generate machine code for an node and needed dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
- std::map<SDNode*, unsigned> &VRBaseMap) {
- unsigned VRBase = 0; // First virtual register for node
-
+ DenseMap<SDOperand, unsigned> &VRBaseMap) {
// If machine instruction
if (Node->isTargetOpcode()) {
unsigned Opc = Node->getTargetOpcode();
#endif
// Create the new machine instruction.
- MachineInstr *MI = new MachineInstr(*TII, Opc, NumMIOperands);
+ MachineInstr *MI = new MachineInstr(II);
// Add result register values for things that are defined by this
// instruction.
-
- // If the node is only used by a CopyToReg and the dest reg is a vreg, use
- // the CopyToReg'd destination register instead of creating a new vreg.
- if (NumResults == 1) {
- for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
- UI != E; ++UI) {
- SDNode *Use = *UI;
- if (Use->getOpcode() == ISD::CopyToReg &&
- Use->getOperand(2).Val == Node) {
- unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(Reg)) {
- VRBase = Reg;
- MI->addRegOperand(Reg, true);
- break;
- }
- }
- }
- }
-
- // Otherwise, create new virtual registers.
- if (NumResults && VRBase == 0)
- VRBase = CreateVirtualRegisters(MRI, MI, NumResults, RegMap, TII, II);
+ if (NumResults)
+ CreateVirtualRegisters(Node, NumResults, MRI, MI, RegMap,
+ TII, II, VRBaseMap);
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
if (CommuteSet.count(Node)) {
MachineInstr *NewMI = TII->commuteInstruction(MI);
if (NewMI == 0)
- DEBUG(std::cerr << "Sched: COMMUTING FAILED!\n");
+ DOUT << "Sched: COMMUTING FAILED!\n";
else {
- DEBUG(std::cerr << "Sched: COMMUTED TO: " << *NewMI);
+ DOUT << "Sched: COMMUTED TO: " << *NewMI;
if (MI != NewMI) {
delete MI;
MI = NewMI;
switch (Node->getOpcode()) {
default:
#ifndef NDEBUG
- Node->dump();
+ Node->dump(&DAG);
#endif
assert(0 && "This target-independent node should have been selected!");
case ISD::EntryToken: // fall thru
case ISD::TokenFactor:
+ case ISD::LABEL:
break;
case ISD::CopyToReg: {
- unsigned InReg = getVR(Node->getOperand(2), VRBaseMap);
+ unsigned InReg;
+ if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(2)))
+ InReg = R->getReg();
+ else
+ InReg = getVR(Node->getOperand(2), VRBaseMap);
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
- if (InReg != DestReg) // Coalesced away the copy?
- MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
- RegMap->getRegClass(InReg));
+ if (InReg != DestReg) {// Coalesced away the copy?
+ const TargetRegisterClass *TRC = 0;
+ // Get the target register class
+ if (MRegisterInfo::isVirtualRegister(InReg))
+ TRC = RegMap->getRegClass(InReg);
+ else
+ TRC = getPhysicalRegisterRegClass(MRI,
+ Node->getOperand(2).getValueType(),
+ InReg);
+ MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC);
+ }
break;
}
case ISD::CopyFromReg: {
+ unsigned VRBase = 0;
unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
if (MRegisterInfo::isVirtualRegister(SrcReg)) {
- VRBase = SrcReg; // Just use the input register directly!
+ // Just use the input register directly!
+ bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0),SrcReg));
+ assert(isNew && "Node emitted out of order - early");
break;
}
if (VRBase) {
TRC = RegMap->getRegClass(VRBase);
} else {
+ TRC = getPhysicalRegisterRegClass(MRI, Node->getValueType(0), SrcReg);
- // Pick the register class of the right type that contains this physreg.
- for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
- E = MRI->regclass_end(); I != E; ++I)
- if ((*I)->hasType(Node->getValueType(0)) &&
- (*I)->contains(SrcReg)) {
- TRC = *I;
- break;
- }
- assert(TRC && "Couldn't find register class for reg copy!");
-
// Create the reg, emit the copy.
VRBase = RegMap->createVirtualRegister(TRC);
}
MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
+
+ bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase));
+ assert(isNew && "Node emitted out of order - early");
break;
}
case ISD::INLINEASM: {
// Create the inline asm machine instruction.
MachineInstr *MI =
- new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
+ new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
// Add the asm string as an external symbol operand.
const char *AsmStr =
}
}
}
-
- assert(!VRBaseMap.count(Node) && "Node emitted out of order - early");
- VRBaseMap[Node] = VRBase;
}
void ScheduleDAG::EmitNoop() {
// Finally, emit the code for all of the scheduled instructions.
- std::map<SDNode*, unsigned> VRBaseMap;
+ DenseMap<SDOperand, unsigned> VRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i]) {
for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
if (SUnit *SU = Sequence[i])
SU->dump(&DAG);
else
- std::cerr << "**** NOOP ****\n";
+ cerr << "**** NOOP ****\n";
}
}
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
/// a group of nodes flagged together.
void SUnit::dump(const SelectionDAG *G) const {
- std::cerr << "SU(" << NodeNum << "): ";
+ cerr << "SU(" << NodeNum << "): ";
Node->dump(G);
- std::cerr << "\n";
+ cerr << "\n";
if (FlaggedNodes.size() != 0) {
for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
- std::cerr << " ";
+ cerr << " ";
FlaggedNodes[i]->dump(G);
- std::cerr << "\n";
+ cerr << "\n";
}
}
}
void SUnit::dumpAll(const SelectionDAG *G) const {
dump(G);
- std::cerr << " # preds left : " << NumPredsLeft << "\n";
- std::cerr << " # succs left : " << NumSuccsLeft << "\n";
- std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
- std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
- std::cerr << " Latency : " << Latency << "\n";
- std::cerr << " Depth : " << Depth << "\n";
- std::cerr << " Height : " << Height << "\n";
+ cerr << " # preds left : " << NumPredsLeft << "\n";
+ cerr << " # succs left : " << NumSuccsLeft << "\n";
+ cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
+ cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
+ cerr << " Latency : " << Latency << "\n";
+ cerr << " Depth : " << Depth << "\n";
+ cerr << " Height : " << Height << "\n";
if (Preds.size() != 0) {
- std::cerr << " Predecessors:\n";
+ cerr << " Predecessors:\n";
for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
I != E; ++I) {
if (I->second)
- std::cerr << " ch #";
+ cerr << " ch #";
else
- std::cerr << " val #";
- std::cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
+ cerr << " val #";
+ cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
}
}
if (Succs.size() != 0) {
- std::cerr << " Successors:\n";
+ cerr << " Successors:\n";
for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
I != E; ++I) {
if (I->second)
- std::cerr << " ch #";
+ cerr << " ch #";
else
- std::cerr << " val #";
- std::cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
+ cerr << " val #";
+ cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
}
}
- std::cerr << "\n";
+ cerr << "\n";
}
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