unsigned ResNo = Use->getOperand(2).ResNo;
if (Def->isTargetOpcode()) {
- const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
- if (ResNo >= II.numDefs &&
- II.ImplicitDefs[ResNo - II.numDefs] == Reg) {
+ const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
+ if (ResNo >= II.getNumDefs() &&
+ II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
PhysReg = Reg;
const TargetRegisterClass *RC =
MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
- for (unsigned i = 0; i != TID.numOperands; ++i) {
+ const TargetInstrDesc &TID = TII->get(Opc);
+ for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
break;
}
}
- if (TID.Flags & M_COMMUTABLE)
+ if (TID.isCommutable())
SU->isCommutable = true;
}
for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
SDNode *N = SU->FlaggedNodes[n];
if (N->isTargetOpcode() &&
- TII->getImplicitDefs(N->getTargetOpcode()) &&
- CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode()))
+ TII->get(N->getTargetOpcode()).getImplicitDefs() &&
+ CountResults(N) > TII->get(N->getTargetOpcode()).getNumDefs())
SU->hasPhysRegDefs = true;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
static const TargetRegisterClass *getInstrOperandRegClass(
const MRegisterInfo *MRI,
const TargetInstrInfo *TII,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc &II,
unsigned Op) {
- if (Op >= II->numOperands) {
- assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
+ if (Op >= II.getNumOperands()) {
+ assert(II.isVariadic() && "Invalid operand # of instruction");
return NULL;
}
- if (II->OpInfo[Op].isLookupPtrRegClass())
+ if (II.OpInfo[Op].isLookupPtrRegClass())
return TII->getPointerRegClass();
- return MRI->getRegClass(II->OpInfo[Op].RegClass);
+ return MRI->getRegClass(II.OpInfo[Op].RegClass);
}
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
MachineInstr *MI,
- const TargetInstrDescriptor &II,
+ const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
- for (unsigned i = 0; i < II.numDefs; ++i) {
+ for (unsigned i = 0; i < II.getNumDefs(); ++i) {
// If the specific node value is only used by a CopyToReg and the dest reg
// is a vreg, use the CopyToReg'd destination register instead of creating
// a new vreg.
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
- const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
+ const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i);
assert(RC && "Isn't a register operand!");
VRBase = RegInfo.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
/// assertions only.
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc *II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- const TargetInstrDescriptor *TID = MI->getDesc();
- bool isOptDef = (IIOpNum < TID->numOperands)
- ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
+ const TargetInstrDesc &TID = MI->getDesc();
+ bool isOptDef = (IIOpNum < TID.getNumOperands())
+ ? (TID.OpInfo[IIOpNum].isOptionalDef()) : false;
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
if (VRC != RC) {
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
assert(RegInfo.getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
return;
}
- const TargetInstrDescriptor &II = TII->get(Opc);
+ const TargetInstrDesc &II = TII->get(Opc);
unsigned NumResults = CountResults(Node);
unsigned NodeOperands = CountOperands(Node);
unsigned NumMIOperands = NodeOperands + NumResults;
- bool HasPhysRegOuts = (NumResults > II.numDefs) && II.ImplicitDefs;
+ bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
+ II.getImplicitDefs() != 0;
#ifndef NDEBUG
- assert((unsigned(II.numOperands) == NumMIOperands ||
- HasPhysRegOuts || (II.Flags & M_VARIABLE_OPS)) &&
+ assert((II.getNumOperands() == NumMIOperands ||
+ HasPhysRegOuts || II.isVariadic()) &&
"#operands for dag node doesn't match .td file!");
#endif
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
for (unsigned i = 0; i != NodeOperands; ++i)
- AddOperand(MI, Node->getOperand(i), i+II.numDefs, &II, VRBaseMap);
+ AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
// Commute node if it has been determined to be profitable.
if (CommuteSet.count(Node)) {
}
// Now that we have emitted all operands, emit this instruction itself.
- if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
+ if (!II.usesCustomDAGSchedInsertionHook()) {
BB->insert(BB->end(), MI);
} else {
// Insert this instruction into the end of the basic block, potentially
// Additional results must be an physical register def.
if (HasPhysRegOuts) {
- for (unsigned i = II.numDefs; i < NumResults; ++i) {
- unsigned Reg = II.ImplicitDefs[i - II.numDefs];
+ for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
+ unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
if (Node->hasAnyUseOfValue(i))
EmitCopyFromReg(Node, i, InstanceNo, Reg, VRBaseMap);
}