#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/MathExtras.h"
using namespace llvm;
+ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
+ const TargetMachine &tm)
+ : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) {
+ TII = TM.getInstrInfo();
+ MRI = TM.getRegisterInfo();
+ ConstPool = BB->getParent()->getConstantPool();
+}
/// CheckForPhysRegDependency - Check if the dependency between def and use of
/// a specified operand is a physical register dependency. If so, returns the
unsigned ResNo = Use->getOperand(2).ResNo;
if (Def->isTargetOpcode()) {
- const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
- if (ResNo >= II.numDefs &&
- II.ImplicitDefs[ResNo - II.numDefs] == Reg) {
+ const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
+ if (ResNo >= II.getNumDefs() &&
+ II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
PhysReg = Reg;
const TargetRegisterClass *RC =
MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
- for (unsigned i = 0; i != TID.numOperands; ++i) {
+ const TargetInstrDesc &TID = TII->get(Opc);
+ for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
break;
}
}
- if (TID.Flags & M_COMMUTABLE)
+ if (TID.isCommutable())
SU->isCommutable = true;
}
for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
SDNode *N = SU->FlaggedNodes[n];
if (N->isTargetOpcode() &&
- TII->getImplicitDefs(N->getTargetOpcode()) &&
- CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode()))
+ TII->get(N->getTargetOpcode()).getImplicitDefs() &&
+ CountResults(N) > TII->get(N->getTargetOpcode()).getNumDefs())
SU->hasPhysRegDefs = true;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
} else {
SU->Latency = 0;
if (SU->Node->isTargetOpcode()) {
- unsigned SchedClass = TII->getSchedClass(SU->Node->getTargetOpcode());
+ unsigned SchedClass =
+ TII->get(SU->Node->getTargetOpcode()).getSchedClass();
InstrStage *S = InstrItins.begin(SchedClass);
InstrStage *E = InstrItins.end(SchedClass);
for (; S != E; ++S)
for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i) {
SDNode *FNode = SU->FlaggedNodes[i];
if (FNode->isTargetOpcode()) {
- unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
+ unsigned SchedClass =TII->get(FNode->getTargetOpcode()).getSchedClass();
InstrStage *S = InstrItins.begin(SchedClass);
InstrStage *E = InstrItins.end(SchedClass);
for (; S != E; ++S)
static const TargetRegisterClass *getInstrOperandRegClass(
const MRegisterInfo *MRI,
const TargetInstrInfo *TII,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc &II,
unsigned Op) {
- if (Op >= II->numOperands) {
- assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
+ if (Op >= II.getNumOperands()) {
+ assert(II.isVariadic() && "Invalid operand # of instruction");
return NULL;
}
- const TargetOperandInfo &toi = II->OpInfo[Op];
- return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
- ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
+ if (II.OpInfo[Op].isLookupPtrRegClass())
+ return TII->getPointerRegClass();
+ return MRI->getRegClass(II.OpInfo[Op].RegClass);
}
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
const TargetRegisterClass *TRC = 0;
// Figure out the register class to create for the destreg.
if (VRBase)
- TRC = RegMap->getRegClass(VRBase);
+ TRC = RegInfo.getRegClass(VRBase);
else
TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg);
VRBase = SrcReg;
} else {
// Create the reg, emit the copy.
- VRBase = RegMap->createVirtualRegister(TRC);
- MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
+ VRBase = RegInfo.createVirtualRegister(TRC);
+ TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
}
if (InstanceNo > 0)
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
MachineInstr *MI,
- const TargetInstrDescriptor &II,
+ const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
- for (unsigned i = 0; i < II.numDefs; ++i) {
+ for (unsigned i = 0; i < II.getNumDefs(); ++i) {
// If the specific node value is only used by a CopyToReg and the dest reg
// is a vreg, use the CopyToReg'd destination register instead of creating
// a new vreg.
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
VRBase = Reg;
- MI->addRegOperand(Reg, true);
+ MI->addOperand(MachineOperand::CreateReg(Reg, true));
break;
}
}
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
- const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
+ const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i);
assert(RC && "Isn't a register operand!");
- VRBase = RegMap->createVirtualRegister(RC);
- MI->addRegOperand(VRBase, true);
+ VRBase = RegInfo.createVirtualRegister(RC);
+ MI->addOperand(MachineOperand::CreateReg(VRBase, true));
}
bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
/// assertions only.
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc *II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
- bool isOptDef = (IIOpNum < TID->numOperands)
- ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
- MI->addRegOperand(VReg, isOptDef);
+ const TargetInstrDesc &TID = MI->getDesc();
+ bool isOptDef = (IIOpNum < TID.getNumOperands())
+ ? (TID.OpInfo[IIOpNum].isOptionalDef()) : false;
+ MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
- const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
+ const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
if (VRC != RC) {
cerr << "Register class of operand and regclass of use don't agree!\n";
#ifndef NDEBUG
abort();
}
}
- } else if (ConstantSDNode *C =
- dyn_cast<ConstantSDNode>(Op)) {
- MI->addImmOperand(C->getValue());
- } else if (RegisterSDNode *R =
- dyn_cast<RegisterSDNode>(Op)) {
- MI->addRegOperand(R->getReg(), false);
- } else if (GlobalAddressSDNode *TGA =
- dyn_cast<GlobalAddressSDNode>(Op)) {
- MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
- } else if (BasicBlockSDNode *BB =
- dyn_cast<BasicBlockSDNode>(Op)) {
- MI->addMachineBasicBlockOperand(BB->getBasicBlock());
- } else if (FrameIndexSDNode *FI =
- dyn_cast<FrameIndexSDNode>(Op)) {
- MI->addFrameIndexOperand(FI->getIndex());
- } else if (JumpTableSDNode *JT =
- dyn_cast<JumpTableSDNode>(Op)) {
- MI->addJumpTableIndexOperand(JT->getIndex());
- } else if (ConstantPoolSDNode *CP =
- dyn_cast<ConstantPoolSDNode>(Op)) {
+ } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateImm(C->getValue()));
+ } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
+ } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
+ } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
+ } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
+ } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
+ } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
int Offset = CP->getOffset();
unsigned Align = CP->getAlignment();
const Type *Type = CP->getType();
Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
else
Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
- MI->addConstantPoolIndexOperand(Idx, Offset);
- } else if (ExternalSymbolSDNode *ES =
- dyn_cast<ExternalSymbolSDNode>(Op)) {
- MI->addExternalSymbolOperand(ES->getSymbol());
+ MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
+ } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
} else {
assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, false);
+ MI->addOperand(MachineOperand::CreateReg(VReg, false));
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == RC &&
+ assert(RegInfo.getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
}
}
// Figure out the register class to create for the destreg.
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
- const TargetRegisterClass *TRC = RegMap->getRegClass(VReg);
+ const TargetRegisterClass *TRC = RegInfo.getRegClass(VReg);
const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
if (VRBase) {
// Grab the destination register
const TargetRegisterClass *DRC = 0;
- DRC = RegMap->getRegClass(VRBase);
+ DRC = RegInfo.getRegClass(VRBase);
assert(SRC == DRC &&
"Source subregister and destination must have the same class");
} else {
// Create the reg
- VRBase = RegMap->createVirtualRegister(SRC);
+ VRBase = RegInfo.createVirtualRegister(SRC);
}
// Add def, source, and subreg index
- MI->addRegOperand(VRBase, true);
+ MI->addOperand(MachineOperand::CreateReg(VRBase, true));
AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
- MI->addImmOperand(SubIdx);
+ MI->addOperand(MachineOperand::CreateImm(SubIdx));
} else if (Opc == TargetInstrInfo::INSERT_SUBREG) {
assert((Node->getNumOperands() == 2 || Node->getNumOperands() == 3) &&
SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
}
- // TODO: Add tracking info to SSARegMap of which vregs are subregs
+ // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
// to allow coalescing in the allocator
// If the node is only used by a CopyToReg and the dest reg is a vreg, use
// Figure out the register class to create for the destreg.
const TargetRegisterClass *TRC = 0;
if (VRBase) {
- TRC = RegMap->getRegClass(VRBase);
+ TRC = RegInfo.getRegClass(VRBase);
} else {
- TRC = getSuperregRegisterClass(RegMap->getRegClass(SubReg),
- SubIdx,
+ TRC = getSuperregRegisterClass(RegInfo.getRegClass(SubReg), SubIdx,
Node->getValueType(0));
assert(TRC && "Couldn't determine register class for insert_subreg");
- VRBase = RegMap->createVirtualRegister(TRC); // Create the reg
+ VRBase = RegInfo.createVirtualRegister(TRC); // Create the reg
}
- MI->addRegOperand(VRBase, true);
+ MI->addOperand(MachineOperand::CreateReg(VRBase, true));
AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
if (!isUndefInput)
AddOperand(MI, Node->getOperand(1), 0, 0, VRBaseMap);
- MI->addImmOperand(SubIdx);
+ MI->addOperand(MachineOperand::CreateImm(SubIdx));
} else
assert(0 && "Node is not a subreg insert or extract");
return;
}
- const TargetInstrDescriptor &II = TII->get(Opc);
+ const TargetInstrDesc &II = TII->get(Opc);
unsigned NumResults = CountResults(Node);
unsigned NodeOperands = CountOperands(Node);
unsigned NumMIOperands = NodeOperands + NumResults;
- bool HasPhysRegOuts = (NumResults > II.numDefs) && II.ImplicitDefs;
+ bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
+ II.getImplicitDefs() != 0;
#ifndef NDEBUG
- assert((unsigned(II.numOperands) == NumMIOperands ||
- HasPhysRegOuts || (II.Flags & M_VARIABLE_OPS)) &&
+ assert((II.getNumOperands() == NumMIOperands ||
+ HasPhysRegOuts || II.isVariadic()) &&
"#operands for dag node doesn't match .td file!");
#endif
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
for (unsigned i = 0; i != NodeOperands; ++i)
- AddOperand(MI, Node->getOperand(i), i+II.numDefs, &II, VRBaseMap);
+ AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
// Commute node if it has been determined to be profitable.
if (CommuteSet.count(Node)) {
}
// Now that we have emitted all operands, emit this instruction itself.
- if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
+ if (!II.usesCustomDAGSchedInsertionHook()) {
BB->insert(BB->end(), MI);
} else {
// Insert this instruction into the end of the basic block, potentially
// Additional results must be an physical register def.
if (HasPhysRegOuts) {
- for (unsigned i = II.numDefs; i < NumResults; ++i) {
- unsigned Reg = II.ImplicitDefs[i - II.numDefs];
+ for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
+ unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
if (Node->hasAnyUseOfValue(i))
EmitCopyFromReg(Node, i, InstanceNo, Reg, VRBaseMap);
}
const TargetRegisterClass *TRC = 0;
// Get the target register class
if (MRegisterInfo::isVirtualRegister(InReg))
- TRC = RegMap->getRegClass(InReg);
+ TRC = RegInfo.getRegClass(InReg);
else
TRC =
MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
InReg);
- MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
+ TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
}
break;
}
// Add the asm string as an external symbol operand.
const char *AsmStr =
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
- MI->addExternalSymbolOperand(AsmStr);
+ MI->addOperand(MachineOperand::CreateES(AsmStr));
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
unsigned NumVals = Flags >> 3;
- MI->addImmOperand(Flags);
+ MI->addOperand(MachineOperand::CreateImm(Flags));
++i; // Skip the ID value.
switch (Flags & 7) {
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, false);
+ MI->addOperand(MachineOperand::CreateReg(Reg, false));
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, true);
+ MI->addOperand(MachineOperand::CreateReg(Reg, true));
}
break;
case 3: { // Immediate.
for (; NumVals; --NumVals, ++i) {
if (ConstantSDNode *CS =
dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
- MI->addImmOperand(CS->getValue());
+ MI->addOperand(MachineOperand::CreateImm(CS->getValue()));
} else if (GlobalAddressSDNode *GA =
dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
- MI->addGlobalAddressOperand(GA->getGlobal(), GA->getOffset());
+ MI->addOperand(MachineOperand::CreateGA(GA->getGlobal(),
+ GA->getOffset()));
} else {
- BasicBlockSDNode *BB =
- cast<BasicBlockSDNode>(Node->getOperand(i));
- MI->addMachineBasicBlockOperand(BB->getBasicBlock());
+ BasicBlockSDNode *BB =cast<BasicBlockSDNode>(Node->getOperand(i));
+ MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
}
}
break;
}
}
assert(I->Reg && "Unknown physical register!");
- MRI->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
+ TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
SU->CopyDstRC, SU->CopySrcRC);
} else {
// Copy from physical register.
assert(I->Reg && "Unknown physical register!");
- unsigned VRBase = RegMap->createVirtualRegister(SU->CopyDstRC);
+ unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC);
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
assert(isNew && "Node emitted out of order - early");
- MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
+ TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
SU->CopyDstRC, SU->CopySrcRC);
}
break;
// block before emitting the code for the block.
MachineFunction &MF = DAG.getMachineFunction();
if (&MF.front() == BB) {
- for (MachineFunction::livein_iterator LI = MF.livein_begin(),
- E = MF.livein_end(); LI != E; ++LI)
+ for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(),
+ E = RegInfo.livein_end(); LI != E; ++LI)
if (LI->second) {
- const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
- MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
+ const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
+ TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
LI->first, RC, RC);
}
}
/// Run - perform scheduling.
///
MachineBasicBlock *ScheduleDAG::Run() {
- TII = TM.getInstrInfo();
- MRI = TM.getRegisterInfo();
- RegMap = BB->getParent()->getSSARegMap();
- ConstPool = BB->getParent()->getConstantPool();
-
Schedule();
return BB;
}
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