fold fp_round(fp_round(x)) -> fp_round(x).

[oota-llvm.git] / lib / CodeGen / SelectionDAG / ScheduleDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index ce0707423e6329ca07dae6f53c367ddca0d5b10a..250298e2d6095e5430747d11a7d5f67cd1fb2b52 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -51,9 +51,9 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op,
 
   unsigned ResNo = Use->getOperand(2).ResNo;
   if (Def->isTargetOpcode()) {
-    const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
-    if (ResNo >= II.numDefs &&
-        II.ImplicitDefs[ResNo - II.numDefs] == Reg) {
+    const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
+    if (ResNo >= II.getNumDefs() &&
+        II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
       PhysReg = Reg;
       const TargetRegisterClass *RC =
         MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
@@ -148,14 +148,14 @@ void ScheduleDAG::BuildSchedUnits() {
     
     if (MainNode->isTargetOpcode()) {
       unsigned Opc = MainNode->getTargetOpcode();
-      const TargetInstrDescriptor &TID = TII->get(Opc);
-      for (unsigned i = 0; i != TID.numOperands; ++i) {
+      const TargetInstrDesc &TID = TII->get(Opc);
+      for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
         if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
           SU->isTwoAddress = true;
           break;
         }
       }
-      if (TID.Flags & M_COMMUTABLE)
+      if (TID.isCommutable())
         SU->isCommutable = true;
     }
     
@@ -166,8 +166,8 @@ void ScheduleDAG::BuildSchedUnits() {
     for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
       SDNode *N = SU->FlaggedNodes[n];
       if (N->isTargetOpcode() &&
-          TII->getImplicitDefs(N->getTargetOpcode()) &&
-          CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode()))
+          TII->get(N->getTargetOpcode()).getImplicitDefs() &&
+          CountResults(N) > TII->get(N->getTargetOpcode()).getNumDefs())
         SU->hasPhysRegDefs = true;
       
       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
@@ -207,7 +207,8 @@ void ScheduleDAG::ComputeLatency(SUnit *SU) {
   } else {
     SU->Latency = 0;
     if (SU->Node->isTargetOpcode()) {
-      unsigned SchedClass = TII->getSchedClass(SU->Node->getTargetOpcode());
+      unsigned SchedClass =
+        TII->get(SU->Node->getTargetOpcode()).getSchedClass();
       InstrStage *S = InstrItins.begin(SchedClass);
       InstrStage *E = InstrItins.end(SchedClass);
       for (; S != E; ++S)
@@ -216,7 +217,7 @@ void ScheduleDAG::ComputeLatency(SUnit *SU) {
     for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i) {
       SDNode *FNode = SU->FlaggedNodes[i];
       if (FNode->isTargetOpcode()) {
-        unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
+        unsigned SchedClass =TII->get(FNode->getTargetOpcode()).getSchedClass();
         InstrStage *S = InstrItins.begin(SchedClass);
         InstrStage *E = InstrItins.end(SchedClass);
         for (; S != E; ++S)
@@ -290,15 +291,15 @@ unsigned ScheduleDAG::CountOperands(SDNode *Node) {
 static const TargetRegisterClass *getInstrOperandRegClass(
         const MRegisterInfo *MRI, 
         const TargetInstrInfo *TII,
-        const TargetInstrDescriptor *II,
+        const TargetInstrDesc &II,
         unsigned Op) {
-  if (Op >= II->numOperands) {
-    assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
+  if (Op >= II.getNumOperands()) {
+    assert(II.isVariadic() && "Invalid operand # of instruction");
     return NULL;
   }
-  const TargetOperandInfo &toi = II->OpInfo[Op];
-  return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
-         ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
+  if (II.OpInfo[Op].isLookupPtrRegClass())
+    return TII->getPointerRegClass();
+  return MRI->getRegClass(II.OpInfo[Op].RegClass);
 }
 
 void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
@@ -359,7 +360,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
   } else {
     // Create the reg, emit the copy.
     VRBase = RegInfo.createVirtualRegister(TRC);
-    MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
+    TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
   }
 
   if (InstanceNo > 0)
@@ -370,9 +371,9 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
 
 void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
                                          MachineInstr *MI,
-                                         const TargetInstrDescriptor &II,
+                                         const TargetInstrDesc &II,
                                      DenseMap<SDOperand, unsigned> &VRBaseMap) {
-  for (unsigned i = 0; i < II.numDefs; ++i) {
+  for (unsigned i = 0; i < II.getNumDefs(); ++i) {
     // If the specific node value is only used by a CopyToReg and the dest reg
     // is a vreg, use the CopyToReg'd destination register instead of creating
     // a new vreg.
@@ -395,7 +396,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
     // Create the result registers for this node and add the result regs to
     // the machine instruction.
     if (VRBase == 0) {
-      const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
+      const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i);
       assert(RC && "Isn't a register operand!");
       VRBase = RegInfo.createVirtualRegister(RC);
       MI->addOperand(MachineOperand::CreateReg(VRBase, true));
@@ -421,7 +422,7 @@ static unsigned getVR(SDOperand Op, DenseMap<SDOperand, unsigned> &VRBaseMap) {
 /// assertions only.
 void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
                              unsigned IIOpNum,
-                             const TargetInstrDescriptor *II,
+                             const TargetInstrDesc *II,
                              DenseMap<SDOperand, unsigned> &VRBaseMap) {
   if (Op.isTargetOpcode()) {
     // Note that this case is redundant with the final else block, but we
@@ -433,16 +434,16 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
     
     // Get/emit the operand.
     unsigned VReg = getVR(Op, VRBaseMap);
-    const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
-    bool isOptDef = (IIOpNum < TID->numOperands)
-      ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
+    const TargetInstrDesc &TID = MI->getDesc();
+    bool isOptDef = (IIOpNum < TID.getNumOperands())
+      ? (TID.OpInfo[IIOpNum].isOptionalDef()) : false;
     MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
     
     // Verify that it is right.
     assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
     if (II) {
       const TargetRegisterClass *RC =
-                          getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+                          getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
       assert(RC && "Don't have operand info for this instruction!");
       const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
       if (VRC != RC) {
@@ -506,7 +507,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
     assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
     if (II) {
       const TargetRegisterClass *RC =
-                            getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+                            getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
       assert(RC && "Don't have operand info for this instruction!");
       assert(RegInfo.getRegClass(VReg) == RC &&
              "Register class of operand and regclass of use don't agree!");
@@ -606,7 +607,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
       SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
     }
     
-    // TODO: Add tracking info to SSARegMap of which vregs are subregs
+    // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
     // to allow coalescing in the allocator
           
     // If the node is only used by a CopyToReg and the dest reg is a vreg, use
@@ -668,15 +669,16 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
       return;
     }
     
-    const TargetInstrDescriptor &II = TII->get(Opc);
+    const TargetInstrDesc &II = TII->get(Opc);
 
     unsigned NumResults = CountResults(Node);
     unsigned NodeOperands = CountOperands(Node);
     unsigned NumMIOperands = NodeOperands + NumResults;
-    bool     HasPhysRegOuts = (NumResults > II.numDefs) && II.ImplicitDefs;
+    bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
+                          II.getImplicitDefs() != 0;
 #ifndef NDEBUG
-    assert((unsigned(II.numOperands) == NumMIOperands ||
-            HasPhysRegOuts || (II.Flags & M_VARIABLE_OPS)) &&
+    assert((II.getNumOperands() == NumMIOperands ||
+            HasPhysRegOuts || II.isVariadic()) &&
            "#operands for dag node doesn't match .td file!"); 
 #endif
 
@@ -691,7 +693,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
     // Emit all of the actual operands of this instruction, adding them to the
     // instruction as appropriate.
     for (unsigned i = 0; i != NodeOperands; ++i)
-      AddOperand(MI, Node->getOperand(i), i+II.numDefs, &II, VRBaseMap);
+      AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
 
     // Commute node if it has been determined to be profitable.
     if (CommuteSet.count(Node)) {
@@ -708,7 +710,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
     }
 
     // Now that we have emitted all operands, emit this instruction itself.
-    if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
+    if (!II.usesCustomDAGSchedInsertionHook()) {
       BB->insert(BB->end(), MI);
     } else {
       // Insert this instruction into the end of the basic block, potentially
@@ -718,8 +720,8 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
 
     // Additional results must be an physical register def.
     if (HasPhysRegOuts) {
-      for (unsigned i = II.numDefs; i < NumResults; ++i) {
-        unsigned Reg = II.ImplicitDefs[i - II.numDefs];
+      for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
+        unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
         if (Node->hasAnyUseOfValue(i))
           EmitCopyFromReg(Node, i, InstanceNo, Reg, VRBaseMap);
       }
@@ -751,7 +753,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
           TRC =
             MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
                                             InReg);
-        MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
+        TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
       }
       break;
     }
@@ -848,7 +850,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM
         }
       }
       assert(I->Reg && "Unknown physical register!");
-      MRI->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
+      TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
                         SU->CopyDstRC, SU->CopySrcRC);
     } else {
       // Copy from physical register.
@@ -856,7 +858,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM
       unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC);
       bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
       assert(isNew && "Node emitted out of order - early");
-      MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
+      TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
                         SU->CopyDstRC, SU->CopySrcRC);
     }
     break;
@@ -874,7 +876,7 @@ void ScheduleDAG::EmitSchedule() {
          E = RegInfo.livein_end(); LI != E; ++LI)
       if (LI->second) {
         const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
-        MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
+        TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
                           LI->first, RC, RC);
       }
   }