#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetInstrItineraries.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Constant.h"
+#include "llvm/Support/MathExtras.h"
#include <iostream>
using namespace llvm;
+/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
+/// This SUnit graph is similar to the SelectionDAG, but represents flagged
+/// together nodes with a single SUnit.
+void ScheduleDAG::BuildSchedUnits() {
+ // Reserve entries in the vector for each of the SUnits we are creating. This
+ // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
+ // invalidated.
+ SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end()));
+
+ const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
+
+ for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
+ E = DAG.allnodes_end(); NI != E; ++NI) {
+ if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
+ continue;
+
+ // If this node has already been processed, stop now.
+ if (SUnitMap[NI]) continue;
+
+ SUnit *NodeSUnit = NewSUnit(NI);
+
+ // See if anything is flagged to this node, if so, add them to flagged
+ // nodes. Nodes can have at most one flag input and one flag output. Flags
+ // are required the be the last operand and result of a node.
+
+ // Scan up, adding flagged preds to FlaggedNodes.
+ SDNode *N = NI;
+ while (N->getNumOperands() &&
+ N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
+ N = N->getOperand(N->getNumOperands()-1).Val;
+ NodeSUnit->FlaggedNodes.push_back(N);
+ SUnitMap[N] = NodeSUnit;
+ }
+
+ // Scan down, adding this node and any flagged succs to FlaggedNodes if they
+ // have a user of the flag operand.
+ N = NI;
+ while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
+ SDOperand FlagVal(N, N->getNumValues()-1);
+
+ // There are either zero or one users of the Flag result.
+ bool HasFlagUse = false;
+ for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
+ UI != E; ++UI)
+ if (FlagVal.isOperand(*UI)) {
+ HasFlagUse = true;
+ NodeSUnit->FlaggedNodes.push_back(N);
+ SUnitMap[N] = NodeSUnit;
+ N = *UI;
+ break;
+ }
+ if (!HasFlagUse) break;
+ }
+
+ // Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
+ // Update the SUnit
+ NodeSUnit->Node = N;
+ SUnitMap[N] = NodeSUnit;
+
+ // Compute the latency for the node. We use the sum of the latencies for
+ // all nodes flagged together into this SUnit.
+ if (InstrItins.isEmpty()) {
+ // No latency information.
+ NodeSUnit->Latency = 1;
+ } else {
+ NodeSUnit->Latency = 0;
+ if (N->isTargetOpcode()) {
+ unsigned SchedClass = TII->getSchedClass(N->getTargetOpcode());
+ InstrStage *S = InstrItins.begin(SchedClass);
+ InstrStage *E = InstrItins.end(SchedClass);
+ for (; S != E; ++S)
+ NodeSUnit->Latency += S->Cycles;
+ }
+ for (unsigned i = 0, e = NodeSUnit->FlaggedNodes.size(); i != e; ++i) {
+ SDNode *FNode = NodeSUnit->FlaggedNodes[i];
+ if (FNode->isTargetOpcode()) {
+ unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
+ InstrStage *S = InstrItins.begin(SchedClass);
+ InstrStage *E = InstrItins.end(SchedClass);
+ for (; S != E; ++S)
+ NodeSUnit->Latency += S->Cycles;
+ }
+ }
+ }
+ }
+
+ // Pass 2: add the preds, succs, etc.
+ for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
+ SUnit *SU = &SUnits[su];
+ SDNode *MainNode = SU->Node;
+
+ if (MainNode->isTargetOpcode()) {
+ unsigned Opc = MainNode->getTargetOpcode();
+ if (TII->isTwoAddrInstr(Opc))
+ SU->isTwoAddress = true;
+ if (TII->isCommutableInstr(Opc))
+ SU->isCommutable = true;
+ }
+
+ // Find all predecessors and successors of the group.
+ // Temporarily add N to make code simpler.
+ SU->FlaggedNodes.push_back(MainNode);
+
+ for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
+ SDNode *N = SU->FlaggedNodes[n];
+
+ for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
+ SDNode *OpN = N->getOperand(i).Val;
+ if (isPassiveNode(OpN)) continue; // Not scheduled.
+ SUnit *OpSU = SUnitMap[OpN];
+ assert(OpSU && "Node has no SUnit!");
+ if (OpSU == SU) continue; // In the same group.
+
+ MVT::ValueType OpVT = N->getOperand(i).getValueType();
+ assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
+ bool isChain = OpVT == MVT::Other;
+
+ if (SU->Preds.insert(std::make_pair(OpSU, isChain)).second) {
+ if (!isChain) {
+ SU->NumPreds++;
+ SU->NumPredsLeft++;
+ } else {
+ SU->NumChainPredsLeft++;
+ }
+ }
+ if (OpSU->Succs.insert(std::make_pair(SU, isChain)).second) {
+ if (!isChain) {
+ OpSU->NumSuccs++;
+ OpSU->NumSuccsLeft++;
+ } else {
+ OpSU->NumChainSuccsLeft++;
+ }
+ }
+ }
+ }
+
+ // Remove MainNode from FlaggedNodes again.
+ SU->FlaggedNodes.pop_back();
+ }
+
+ return;
+}
+
+static void CalculateDepths(SUnit *SU, unsigned Depth, unsigned Max) {
+ if (Depth > SU->Depth) {
+ SU->Depth = Depth;
+ for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Succs.begin(),
+ E = SU->Succs.end(); I != E; ++I)
+ CalculateDepths(I->first, Depth+1, Max);
+ }
+}
+
+void ScheduleDAG::CalculateDepths() {
+ SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
+ ::CalculateDepths(Entry, 0U, SUnits.size());
+ for (unsigned i = 0, e = SUnits.size(); i != e; ++i)
+ if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
+ ::CalculateDepths(&SUnits[i], 0U, SUnits.size());
+ }
+}
+
+static void CalculateHeights(SUnit *SU, unsigned Height) {
+ if (Height > SU->Height) {
+ SU->Height = Height;
+ for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
+ E = SU->Preds.end(); I != E; ++I)
+ CalculateHeights(I->first, Height+1);
+ }
+}
+void ScheduleDAG::CalculateHeights() {
+ SUnit *Root = SUnitMap[DAG.getRoot().Val];
+ ::CalculateHeights(Root, 0U);
+}
+
/// CountResults - The results of target nodes have register or immediate
/// operands first, then an optional chain, and optional flag operands (which do
/// not go into the machine instrs.)
}
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op)) {
- MI->addZeroExtImm64Operand(C->getValue());
+ MI->addImmOperand(C->getValue());
} else if (RegisterSDNode*R =
dyn_cast<RegisterSDNode>(Op)) {
MI->addRegOperand(R->getReg(), MachineOperand::Use);
} else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) {
- MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
+ MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
} else if (BasicBlockSDNode *BB =
dyn_cast<BasicBlockSDNode>(Op)) {
MI->addMachineBasicBlockOperand(BB->getBasicBlock());
} else if (FrameIndexSDNode *FI =
dyn_cast<FrameIndexSDNode>(Op)) {
MI->addFrameIndexOperand(FI->getIndex());
+ } else if (JumpTableSDNode *JT =
+ dyn_cast<JumpTableSDNode>(Op)) {
+ MI->addJumpTableIndexOperand(JT->getIndex());
} else if (ConstantPoolSDNode *CP =
dyn_cast<ConstantPoolSDNode>(Op)) {
int Offset = CP->getOffset();
if (Align == 0) {
if (CP->get()->getType() == Type::DoubleTy)
Align = 3; // always 8-byte align doubles.
- else
+ else {
Align = TM.getTargetData()
- .getTypeAlignmentShift(CP->get()->getType());
+ ->getTypeAlignmentShift(CP->get()->getType());
+ if (Align == 0) {
+ // Alignment of packed types. FIXME!
+ Align = TM.getTargetData()->getTypeSize(CP->get()->getType());
+ Align = Log2_64(Align);
+ }
+ }
}
unsigned Idx = ConstPool->getConstantPoolIndex(CP->get(), Align);
MI->addConstantPoolIndexOperand(Idx, Offset);
} else if (ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Op)) {
- MI->addExternalSymbolOperand(ES->getSymbol(), false);
+ MI->addExternalSymbolOperand(ES->getSymbol());
} else {
assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Flag &&
#endif
// Create the new machine instruction.
- MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
+ MachineInstr *MI = new MachineInstr(Opc, NumMIOperands);
// Add result register values for things that are defined by this
// instruction.
// instruction as appropriate.
for (unsigned i = 0; i != NodeOperands; ++i)
AddOperand(MI, Node->getOperand(i), i+NumResults, &II, VRBaseMap);
-
+
+ // Commute node if it has been determined to be profitable.
+ if (CommuteSet.count(Node)) {
+ MachineInstr *NewMI = TII->commuteInstruction(MI);
+ if (NewMI == 0)
+ DEBUG(std::cerr << "Sched: COMMUTING FAILED!\n");
+ else {
+ DEBUG(std::cerr << "Sched: COMMUTED TO: " << *NewMI);
+ MI = NewMI;
+ }
+ }
+
// Now that we have emitted all operands, emit this instruction itself.
if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
BB->insert(BB->end(), MI);
case ISD::CopyToReg: {
unsigned InReg = getVR(Node->getOperand(2), VRBaseMap);
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
- if (InReg != DestReg) // Coallesced away the copy?
+ if (InReg != DestReg) // Coalesced away the copy?
MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
RegMap->getRegClass(InReg));
break;
// Add the asm string as an external symbol operand.
const char *AsmStr =
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
- MI->addExternalSymbolOperand(AsmStr, false);
+ MI->addExternalSymbolOperand(AsmStr);
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
unsigned NumVals = Flags >> 3;
- MI->addZeroExtImm64Operand(Flags);
+ MI->addImmOperand(Flags);
++i; // Skip the ID value.
switch (Flags & 7) {
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addMachineRegOperand(Reg, MachineOperand::Use);
+ MI->addRegOperand(Reg, MachineOperand::Use);
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addMachineRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, MachineOperand::Def);
}
break;
case 3: { // Immediate.
assert(NumVals == 1 && "Unknown immediate value!");
uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
- MI->addZeroExtImm64Operand(Val);
+ MI->addImmOperand(Val);
++i;
break;
}
TII->insertNoop(*BB, BB->end());
}
+/// EmitSchedule - Emit the machine code in scheduled order.
+void ScheduleDAG::EmitSchedule() {
+ std::map<SDNode*, unsigned> VRBaseMap;
+ for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
+ if (SUnit *SU = Sequence[i]) {
+ for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
+ EmitNode(SU->FlaggedNodes[j], VRBaseMap);
+ EmitNode(SU->Node, VRBaseMap);
+ } else {
+ // Null SUnit* is a noop.
+ EmitNoop();
+ }
+ }
+}
+
+/// dump - dump the schedule.
+void ScheduleDAG::dumpSchedule() const {
+ for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
+ if (SUnit *SU = Sequence[i])
+ SU->dump(&DAG);
+ else
+ std::cerr << "**** NOOP ****\n";
+ }
+}
+
+
/// Run - perform scheduling.
///
MachineBasicBlock *ScheduleDAG::Run() {
RegMap = BB->getParent()->getSSARegMap();
ConstPool = BB->getParent()->getConstantPool();
- // Number the nodes
- NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
-
Schedule();
return BB;
}
+/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
+/// a group of nodes flagged together.
+void SUnit::dump(const SelectionDAG *G) const {
+ std::cerr << "SU(" << NodeNum << "): ";
+ Node->dump(G);
+ std::cerr << "\n";
+ if (FlaggedNodes.size() != 0) {
+ for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
+ std::cerr << " ";
+ FlaggedNodes[i]->dump(G);
+ std::cerr << "\n";
+ }
+ }
+}
+
+void SUnit::dumpAll(const SelectionDAG *G) const {
+ dump(G);
+
+ std::cerr << " # preds left : " << NumPredsLeft << "\n";
+ std::cerr << " # succs left : " << NumSuccsLeft << "\n";
+ std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
+ std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
+ std::cerr << " Latency : " << Latency << "\n";
+ std::cerr << " Depth : " << Depth << "\n";
+ std::cerr << " Height : " << Height << "\n";
+ if (Preds.size() != 0) {
+ std::cerr << " Predecessors:\n";
+ for (std::set<std::pair<SUnit*,bool> >::const_iterator I = Preds.begin(),
+ E = Preds.end(); I != E; ++I) {
+ if (I->second)
+ std::cerr << " ch ";
+ else
+ std::cerr << " val ";
+ I->first->dump(G);
+ }
+ }
+ if (Succs.size() != 0) {
+ std::cerr << " Successors:\n";
+ for (std::set<std::pair<SUnit*, bool> >::const_iterator I = Succs.begin(),
+ E = Succs.end(); I != E; ++I) {
+ if (I->second)
+ std::cerr << " ch ";
+ else
+ std::cerr << " val ";
+ I->first->dump(G);
+ }
+ }
+ std::cerr << "\n";
+}
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