//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "sched"
+#include "llvm/Type.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
-static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) {
- std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
+static unsigned getVR(SDOperand Op, DenseMap<SDNode*, unsigned> &VRBaseMap) {
+ DenseMap<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
return I->second + Op.ResNo;
}
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
const TargetInstrDescriptor *II,
- std::map<SDNode*, unsigned> &VRBaseMap) {
+ DenseMap<SDNode*, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
const TargetRegisterClass *RC =
getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == RC &&
- "Register class of operand and regclass of use don't agree!");
+ const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
+ if (VRC != RC) {
+ cerr << "Register class of operand and regclass of use don't agree!\n";
+#ifndef NDEBUG
+ cerr << "Operand = " << IIOpNum << "\n";
+ cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
+ cerr << "MI = "; MI->print(cerr);
+ cerr << "VReg = " << VReg << "\n";
+ cerr << "VReg RegClass size = " << VRC->getSize()
+ << ", align = " << VRC->getAlignment() << "\n";
+ cerr << "Expected RegClass size = " << RC->getSize()
+ << ", align = " << RC->getAlignment() << "\n";
+#endif
+ cerr << "Fatal error, aborting.\n";
+ abort();
+ }
}
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op)) {
const Type *Type = CP->getType();
// MachineConstantPool wants an explicit alignment.
if (Align == 0) {
- if (Type == Type::DoubleTy)
- Align = 3; // always 8-byte align doubles.
- else {
- Align = TM.getTargetData()->getTypeAlignmentShift(Type);
- if (Align == 0) {
- // Alignment of packed types. FIXME!
- Align = TM.getTargetData()->getTypeSize(Type);
- Align = Log2_64(Align);
- }
+ Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
+ if (Align == 0) {
+ // Alignment of vector types. FIXME!
+ Align = TM.getTargetData()->getTypeSize(Type);
+ Align = Log2_64(Align);
}
}
}
+// Returns the Register Class of a physical register
+static const TargetRegisterClass *getPhysicalRegisterRegClass(
+ const MRegisterInfo *MRI,
+ MVT::ValueType VT,
+ unsigned reg) {
+ assert(MRegisterInfo::isPhysicalRegister(reg) &&
+ "reg must be a physical register");
+ // Pick the register class of the right type that contains this physreg.
+ for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
+ E = MRI->regclass_end(); I != E; ++I)
+ if ((*I)->hasType(VT) && (*I)->contains(reg))
+ return *I;
+ assert(false && "Couldn't find the register class");
+ return 0;
+}
/// EmitNode - Generate machine code for an node and needed dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
- std::map<SDNode*, unsigned> &VRBaseMap) {
+ DenseMap<SDNode*, unsigned> &VRBaseMap) {
unsigned VRBase = 0; // First virtual register for node
// If machine instruction
switch (Node->getOpcode()) {
default:
#ifndef NDEBUG
- Node->dump();
+ Node->dump(&DAG);
#endif
assert(0 && "This target-independent node should have been selected!");
case ISD::EntryToken: // fall thru
case ISD::TokenFactor:
+ case ISD::LABEL:
break;
case ISD::CopyToReg: {
unsigned InReg;
else
InReg = getVR(Node->getOperand(2), VRBaseMap);
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
- if (InReg != DestReg) // Coalesced away the copy?
- MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
- RegMap->getRegClass(InReg));
+ if (InReg != DestReg) {// Coalesced away the copy?
+ const TargetRegisterClass *TRC = 0;
+ // Get the target register class
+ if (MRegisterInfo::isVirtualRegister(InReg))
+ TRC = RegMap->getRegClass(InReg);
+ else
+ TRC = getPhysicalRegisterRegClass(MRI,
+ Node->getOperand(2).getValueType(),
+ InReg);
+ MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC);
+ }
break;
}
case ISD::CopyFromReg: {
if (VRBase) {
TRC = RegMap->getRegClass(VRBase);
} else {
+ TRC = getPhysicalRegisterRegClass(MRI, Node->getValueType(0), SrcReg);
- // Pick the register class of the right type that contains this physreg.
- for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
- E = MRI->regclass_end(); I != E; ++I)
- if ((*I)->hasType(Node->getValueType(0)) &&
- (*I)->contains(SrcReg)) {
- TRC = *I;
- break;
- }
- assert(TRC && "Couldn't find register class for reg copy!");
-
// Create the reg, emit the copy.
VRBase = RegMap->createVirtualRegister(TRC);
}
// Finally, emit the code for all of the scheduled instructions.
- std::map<SDNode*, unsigned> VRBaseMap;
+ DenseMap<SDNode*, unsigned> VRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i]) {
for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
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