//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "sched"
+#include "llvm/Type.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
-#include <iostream>
using namespace llvm;
-
/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
/// This SUnit graph is similar to the SelectionDAG, but represents flagged
/// together nodes with a single SUnit.
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
for (unsigned i = 0, ee = TII->getNumOperands(Opc); i != ee; ++i) {
- if (TII->getOperandConstraint(Opc, i,
- TargetInstrInfo::TIED_TO) != -1) {
+ if (TII->getOperandConstraint(Opc, i, TOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
break;
}
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
-static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) {
- std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
+static unsigned getVR(SDOperand Op, DenseMap<SDNode*, unsigned> &VRBaseMap) {
+ DenseMap<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
return I->second + Op.ResNo;
}
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
const TargetInstrDescriptor *II,
- std::map<SDNode*, unsigned> &VRBaseMap) {
+ DenseMap<SDNode*, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
const TargetRegisterClass *RC =
getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == RC &&
- "Register class of operand and regclass of use don't agree!");
+ const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
+ if (VRC != RC) {
+ cerr << "Register class of operand and regclass of use don't agree!\n";
+#ifndef NDEBUG
+ cerr << "Operand = " << IIOpNum << "\n";
+ cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
+ cerr << "MI = "; MI->print(cerr);
+ cerr << "VReg = " << VReg << "\n";
+ cerr << "VReg RegClass size = " << VRC->getSize()
+ << ", align = " << VRC->getAlignment() << "\n";
+ cerr << "Expected RegClass size = " << RC->getSize()
+ << ", align = " << RC->getAlignment() << "\n";
+#endif
+ cerr << "Fatal error, aborting.\n";
+ abort();
+ }
}
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op)) {
MI->addImmOperand(C->getValue());
- } else if (RegisterSDNode*R =
+ } else if (RegisterSDNode *R =
dyn_cast<RegisterSDNode>(Op)) {
MI->addRegOperand(R->getReg(), false);
} else if (GlobalAddressSDNode *TGA =
const Type *Type = CP->getType();
// MachineConstantPool wants an explicit alignment.
if (Align == 0) {
- if (Type == Type::DoubleTy)
- Align = 3; // always 8-byte align doubles.
- else {
- Align = TM.getTargetData()->getTypeAlignmentShift(Type);
- if (Align == 0) {
- // Alignment of packed types. FIXME!
- Align = TM.getTargetData()->getTypeSize(Type);
- Align = Log2_64(Align);
- }
+ Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
+ if (Align == 0) {
+ // Alignment of vector types. FIXME!
+ Align = TM.getTargetData()->getTypeSize(Type);
+ Align = Log2_64(Align);
}
}
}
+// Returns the Register Class of a physical register
+static const TargetRegisterClass *getPhysicalRegisterRegClass(
+ const MRegisterInfo *MRI,
+ MVT::ValueType VT,
+ unsigned reg) {
+ assert(MRegisterInfo::isPhysicalRegister(reg) &&
+ "reg must be a physical register");
+ // Pick the register class of the right type that contains this physreg.
+ for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
+ E = MRI->regclass_end(); I != E; ++I)
+ if ((*I)->hasType(VT) && (*I)->contains(reg))
+ return *I;
+ assert(false && "Couldn't find the register class");
+ return 0;
+}
/// EmitNode - Generate machine code for an node and needed dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
- std::map<SDNode*, unsigned> &VRBaseMap) {
+ DenseMap<SDNode*, unsigned> &VRBaseMap) {
unsigned VRBase = 0; // First virtual register for node
// If machine instruction
#endif
// Create the new machine instruction.
- MachineInstr *MI = new MachineInstr(Opc, NumMIOperands);
+ MachineInstr *MI = new MachineInstr(II);
// Add result register values for things that are defined by this
// instruction.
if (CommuteSet.count(Node)) {
MachineInstr *NewMI = TII->commuteInstruction(MI);
if (NewMI == 0)
- DEBUG(std::cerr << "Sched: COMMUTING FAILED!\n");
+ DOUT << "Sched: COMMUTING FAILED!\n";
else {
- DEBUG(std::cerr << "Sched: COMMUTED TO: " << *NewMI);
+ DOUT << "Sched: COMMUTED TO: " << *NewMI;
if (MI != NewMI) {
delete MI;
MI = NewMI;
switch (Node->getOpcode()) {
default:
#ifndef NDEBUG
- Node->dump();
+ Node->dump(&DAG);
#endif
assert(0 && "This target-independent node should have been selected!");
case ISD::EntryToken: // fall thru
case ISD::TokenFactor:
+ case ISD::LABEL:
break;
case ISD::CopyToReg: {
- unsigned InReg = getVR(Node->getOperand(2), VRBaseMap);
+ unsigned InReg;
+ if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(2)))
+ InReg = R->getReg();
+ else
+ InReg = getVR(Node->getOperand(2), VRBaseMap);
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
- if (InReg != DestReg) // Coalesced away the copy?
- MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
- RegMap->getRegClass(InReg));
+ if (InReg != DestReg) {// Coalesced away the copy?
+ const TargetRegisterClass *TRC = 0;
+ // Get the target register class
+ if (MRegisterInfo::isVirtualRegister(InReg))
+ TRC = RegMap->getRegClass(InReg);
+ else
+ TRC = getPhysicalRegisterRegClass(MRI,
+ Node->getOperand(2).getValueType(),
+ InReg);
+ MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC);
+ }
break;
}
case ISD::CopyFromReg: {
if (VRBase) {
TRC = RegMap->getRegClass(VRBase);
} else {
+ TRC = getPhysicalRegisterRegClass(MRI, Node->getValueType(0), SrcReg);
- // Pick the register class of the right type that contains this physreg.
- for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
- E = MRI->regclass_end(); I != E; ++I)
- if ((*I)->hasType(Node->getValueType(0)) &&
- (*I)->contains(SrcReg)) {
- TRC = *I;
- break;
- }
- assert(TRC && "Couldn't find register class for reg copy!");
-
// Create the reg, emit the copy.
VRBase = RegMap->createVirtualRegister(TRC);
}
// Create the inline asm machine instruction.
MachineInstr *MI =
- new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
+ new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
// Add the asm string as an external symbol operand.
const char *AsmStr =
// Finally, emit the code for all of the scheduled instructions.
- std::map<SDNode*, unsigned> VRBaseMap;
+ DenseMap<SDNode*, unsigned> VRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i]) {
for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
if (SUnit *SU = Sequence[i])
SU->dump(&DAG);
else
- std::cerr << "**** NOOP ****\n";
+ cerr << "**** NOOP ****\n";
}
}
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
/// a group of nodes flagged together.
void SUnit::dump(const SelectionDAG *G) const {
- std::cerr << "SU(" << NodeNum << "): ";
+ cerr << "SU(" << NodeNum << "): ";
Node->dump(G);
- std::cerr << "\n";
+ cerr << "\n";
if (FlaggedNodes.size() != 0) {
for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
- std::cerr << " ";
+ cerr << " ";
FlaggedNodes[i]->dump(G);
- std::cerr << "\n";
+ cerr << "\n";
}
}
}
void SUnit::dumpAll(const SelectionDAG *G) const {
dump(G);
- std::cerr << " # preds left : " << NumPredsLeft << "\n";
- std::cerr << " # succs left : " << NumSuccsLeft << "\n";
- std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
- std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
- std::cerr << " Latency : " << Latency << "\n";
- std::cerr << " Depth : " << Depth << "\n";
- std::cerr << " Height : " << Height << "\n";
+ cerr << " # preds left : " << NumPredsLeft << "\n";
+ cerr << " # succs left : " << NumSuccsLeft << "\n";
+ cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
+ cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
+ cerr << " Latency : " << Latency << "\n";
+ cerr << " Depth : " << Depth << "\n";
+ cerr << " Height : " << Height << "\n";
if (Preds.size() != 0) {
- std::cerr << " Predecessors:\n";
+ cerr << " Predecessors:\n";
for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
I != E; ++I) {
if (I->second)
- std::cerr << " ch #";
+ cerr << " ch #";
else
- std::cerr << " val #";
- std::cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
+ cerr << " val #";
+ cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
}
}
if (Succs.size() != 0) {
- std::cerr << " Successors:\n";
+ cerr << " Successors:\n";
for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
I != E; ++I) {
if (I->second)
- std::cerr << " ch #";
+ cerr << " ch #";
else
- std::cerr << " val #";
- std::cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
+ cerr << " val #";
+ cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
}
}
- std::cerr << "\n";
+ cerr << "\n";
}
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